LE28FV4001T 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LE28FV4001T Datasheet PDF : 14 Pages
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LE28FV4001M, T, R-20/25
AC Electrical Characteristics at Ta = 0 to +70°C, VDD = 3.3 V ± 0.3 V
AC Testing Conditions (See Figure 13)
Input rise and fall times: ................10 ns (max)
Output load: ....................................1 TTL gate + 30 pF
Read Cycle
Parameter
Read cycle time
CE access time
Address access time
OE access time
Output low-impedance time from CE
Output low-impedance time from OE
Output high-impedance time from CE
Output high-impedance time from OE
Output valid time from address input
LE28FV4001M, T, R
Symbol
-20
-25
Unit
min
max
min
max
tRC
200
250
ns
tCE
200
250
ns
tAA
200
250
ns
tOE
100
120
ns
tCLZ
0
0
ns
tOLZ
0
0
ns
tCHZ
60
60
ns
tOHZ
60
60
ns
tOH
0
0
ns
Erase/Programming Cycles
LE28FV4001M, T, R
Parameter
Symbol
-20
-25
Unit
min
max
min
max
Sector erase cycle time
Byte programming cycle time
Address setup time
Address hold time
CE and WE setup time
CE and WE hold time
OE setup time
OE hold time
CE pulse width
WE pulse width
WE standby pulse width
CE standby pulse width
Data setup time
Data hold time
Reset recovery time
CE pulse width in protect mode
CE hold time in protect mode
Address setup time in protect mode
Address hold time in protect mode
tSE
4
4
ms
tBP
35
35
µs
tAS
0
0
ns
tAH
50
100
ns
tCS
0
0
ns
tCH
0
0
ns
tOES
10
20
ns
tOEH
10
20
ns
tCP
100
160
ns
tWP
100
160
ns
tWPH
50
50
ns
tCPH
50
50
ns
tDS
50
100
ns
tDH
10
20
ns
tRST
4
4
µs
tPCP
100
100
ns
tPCH
150
150
ns
tPAS
30
30
ns
tPAH
100
100
ns
Note: All signals must hold valid logic levels during the setup and hold periods.
No. 5409-8/14
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