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AS1105 Datasheet PDF : 12 Pages
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Data Sheet AS1105
Decode-Mode Register
In the AS1105 a BCD decoder is included. Every digit can
be selected via register 09h to be decoded. The BCD code
consists of the numbers 0-9, E,H, L,P and -. In register 09h
a logic high enables the decoder for the appropriate digit. In
case that the decoder is bypassed (logic low) the data Bits
D7-D0 correspond to the segment lines of the AS1105. In
table 4 some possible settings for register 09h are shown.
Bit D7, which corresponds to the decimal point, is not
affected by the settings of the decoder. Logic high means
that the decimal point is displayed. In table 5 the font of the
Code B decoder is shown. In table 6 the correspondence of
the register to the appropriate segments of a 7 segment
display is shown (see figure 2)
Intensity Control and Interdigit Blanking
Brightness of the display can be controlled in an analog way
by changing the external resistor (RSET). The current, which
flows between VDD and ISET, defines the current that flows
through the LEDs. The LED current is 100 times the ISET
current. The minimum value of RSET should be 9.53kΩ,
which corresponds to 40mA segment current. The
brightness of the display can also be controlled digitally via
register 0Ah. The brightness can be programmed in 16
steps and is shown in table 7. An internal pulse width
modulator controls the intensity of the display.
Scan-Limit Register
The scan limit register 0Bh selects the number of digits
displayed. When all 4 digits are displayed the update
frequency is typically 800Hz. If the number of digits
displayed is reduced, the update frequency is reduced as
well. The frequency can be calculated using 8fOSC/N,
where N is the number of digits. Since the number of
displayed digits influences the brightness, the resistor RSET
should be adjusted accordingly. Table 9 shows the
maximum allowed current, when fewer than 4 digits are
used. To avoid differences in brightness the scan limit
register should not be used to blank portions of the display
(leading zeros).
Register
Address
D15–D12 D11 D10 D9 D8
No-Op
X
0 0 00
Digit 0
X
0 0 01
Digit 1
X
0 0 10
Digit 2
X
0 0 11
Digit 3
X
0 1 00
Decode
Mode
X
1 0 01
Intensity
X
1 0 10
Scan Limit
X
1 0 11
Shutdown
X
1 1 00
Not used
X
1 1 01
Reset and
ext. Clock
X
1 1 10
Display
Test
X
1 1 11
Hex
Code
0xX0
0xX1
0xX2
0xX3
0xX4
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
Table 2: Register address map
Mode
Shutdown
Mode
Normal
Operation
Address Code
Register Data
(Hex) D7 D6 D5 D4 D3 D2 D1 D0
0xXC
XXXXXXX0
0xXC
XXXXXXX1
Table 3: Shutdown register format (address (hex) = 0xXC)
Decode Mode
D7
D6
Register Data
D5 D4 D3 D2
D1
D0 Hex Code
No decode for digits 4–0 0 0 0 0 0 0 0 0 0x00
Code B decode for digit 0
No decode for digits 4–1
0
0
0
0
0
0
0
1
0x01
Code B decode for digits
3–0
00001111
0x0F
Code B decode for digits
4–0
11111111
0xFF
Table 4: Decode-mode register examples (address (hex) = 0xX9)
Revision 1.32, Oct. 2004
Page 5 of 12
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