2SK3813 데이터 시트보기 (PDF) - Renesas Electronics

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2SK3813

SWITCHING N-CHANNEL POWER MOS FET

Renesas Electronics 

2SK3813

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

Gate Leakage Current

Gate Cut-off Voltage

Forward Transfer Admittance Note

Drain to Source On-state Resistance Note

IDSS

IGSS

VGS(off)

| yfs |

RDS(on)1

RDS(on)2

VDS = 40 V, VGS = 0 V

VGS = ±20 V, VDS = 0 V

VDS = 10 V, ID = 1 mA

VDS = 10 V, ID = 30 A

VGS = 10 V, ID = 30 A

VGS = 4.5 V, ID = 30 A

Input Capacitance

Ciss

VDS = 10 V

Output Capacitance

Reverse Transfer Capacitance

Turn-on Delay Time

Coss

Crss

td(on)

VGS = 0 V

f = 1 MHz

VDD = 20 V, ID = 30 A

Rise Time

Turn-off Delay Time

tr

td(off)

VGS = 10 V

RG = 0 Ω

Fall Time

Total Gate Charge

tf

QG

VDD = 32 V

Gate to Source Charge

QGS

VGS = 10 V

Gate to Drain Charge

Body Diode Forward Voltage Note

Reverse Recovery Time

Reverse Recovery Charge

Note Pulsed

QGD

VF(S-D)

trr

Qrr

ID = 60 A

IF = 60 A, VGS = 0 V

IF = 60 A, VGS = 0 V

di/dt = 100 A/μs

MIN.

1.5

21

TYP.

2.0

42

4.2

5.3

5500

740

490

25

8.5

81

10

96

18

23.5

0.94

35

31

MAX.

10

±100

2.5

5.3

7.1

1.5

UNIT

μA

nA

V

S

mΩ

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

V

ns

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = 20 → 0 V

BVDSS

IAS

ID

VDD

VDS

Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

RG

PG.

VGS

0

τ

τ = 1 μs

Duty Cycle ≤ 1%

RL

VDD

VGS

VGS

Wave Form

10%

0

VDS

90%

VDS

VDS

0

Wave Form

td(on)

VGS

90%

90%

10% 10%

tr td(off) tf

ton

toff

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D16739EJ3V0DS

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