MCP6S91 데이터 시트보기 (PDF) - Microchip Technology
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MCP6S91 Datasheet PDF : 40 Pages
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MCP6S91/2/3
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min Typ Max Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
VIL
0
— 0.3VDD V
IIL
-1.0
—
+1.0 µA
VIH
0.7 VDD
—
VDD
V
—
-1.0
—
1.0
µA In Shutdown mode
SPI Output (SO, for MCP6S93)
Logic Threshold, Low
Logic Threshold, High
SPI Timing
VOL_DIG
VOH_DIG
VSS
VDD – 0.5
— VSS+0.4 V IOL = 2.1 mA, VDD = 5V
—
VDD
V IOH = -400 µA
Pin Capacitance
CPIN
—
10
—
pF All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
tRFI
—
—
2
µs (Note 1)
Output Rise/Fall Times (SO)
tRFO
—
5
—
ns MCP6S93
CS High Time
tCSH
40
—
—
ns
SCK Edge to CS Fall Setup Time
tCS0
10
—
—
ns SCK edge when CS is high
CS Fall to First SCK Edge Setup Time tCSSC
40
—
—
ns
SCK Frequency
fSCK
—
—
10
MHz VDD = 5V (Note 2)
SCK High Time
tHI
40
—
—
ns
SCK Low Time
tLO
40
—
—
ns
SCK Last Edge to CS Rise Setup Time tSCCS
30
—
—
ns
CS Rise to SCK Edge Setup Time
tCS1
100
—
—
ns SCK edge when CS is high
SI Setup Time
tSU
40
—
—
ns
SI Hold Time
tHD
10
—
—
ns
SCK to SO Valid Propagation Delay
tDO
—
—
80
ns MCP6S93
CS Rise to SO Forced to Zero
tSOZ
—
—
80
ns MCP6S93
Channel and Gain Select Timing
Channel Select Time
Gain Select Time
Shutdown Mode Timing
tCH
—
1.5
—
µs CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CS = 0.7 VDD to VOUT 90% point
tG
—
1
—
µs CHx = CHy = 0.3V,
G = 5 to G = 1 select,
CS = 0.7 VDD to VOUT 90% point
Out of Shutdown mode (CS goes high)
tON
to Amplifier Output Turn-on Time
—
3.5
10
µs CS = 0.7 VDD to VOUT 90% point
Into Shutdown mode (CS goes high) to tOFF
Amplifier Output High-Z Turn-off Time
—
1.5
—
µs CS = 0.7 VDD to VOUT 90% point
Note 1:
2:
Not tested in production. Set by design and characterization.
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO ≤ 80 ns), data input set-up time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns) and SCK rise and
fall times of 5 ns. Maximum fSCK is therefore ≈ 5.8 MHz.
2004 Microchip Technology Inc.
DS21908A-page 5
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