MCP6S91 데이터 시트보기 (PDF) - Microchip Technology

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MCP6S91

Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

Microchip Technology 

MCP6S91/2/3

CS

tCH

CS

tG

VOUT

0.6V

0.3V

FIGURE 1-1:

Diagram.

Channel Select Timing

VOUT

1.5V

0.3V

FIGURE 1-3:

Diagram.

Gain Select Timing

CS

tON

tOFF

VOUT

Hi-Z

0.3V

Hi-Z

ISS

30 pA (typ.)

1.0 mA (typ.)

FIGURE 1-2:

PGA Shutdown Timing

Diagram (must enter correct commands before

CS goes high).

CS

SCK

SI

SO

FIGURE 1-4:

tCSSC

tSU tHD

tLO tHI

1/fSCK

tCSH

tSCCS tCS1

tCS0

tDO

tSOZ

(first 16 bits out are always zeros)

Detailed SPI™ Serial Interface Timing; SPI 0,0 Mode.

 2004 Microchip Technology Inc.

DS21908A-page 7

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