MCP6S91 데이터 시트보기 (PDF) - Microchip Technology

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MCP6S91

Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

Microchip Technology 

VOUT (V)

VDD

VDD – 0.3

V2

0.3

V1

0

0.3

0G

VIN (V)

VDD – 0.3 VDD

GG

FIGURE 1-6:

Output Voltage Model with

the standard condition VREF = VSS = 0V.

1.1.3 OUTPUT NON-LINEARITY

Figure 1-7 shows the Integral Non-Linearity (INL) of the

output voltage.

EQUATION 1-5:

INL = VOUT – VO_LIN

The output non-linearity specification in the Electrical

Specifications (with units of: % of FSR) is related to

Figure 1-7 by:

EQUATION 1-6:

VONL

=

-m----a----x---(--V----3--,---V----4---) ⋅ 100%

VDD – 0.6V

The Full-Scale Range (FSR) is VDD – 0.6V

(0.3V to VDD – 0.3V).

INL (V)

MCP6S91/2/3

1.1.4

DIFFERENT VREF CONDITIONS

Some of the plots in Section 2.0 “Typical Performance

Curves”, have the conditions VREF = VDD/2 or

VREF = VDD. The equations and figures above are easily

modified for these conditions. The ideal VOUT equation

becomes:

EQUATION 1-7:

VO_ID = VREF + G(VIN – VREF)

VDD ≥ VREF > VSS = 0V

The complete linear model is:

EQUATION 1-8:

VON_LIN = G(1 + gE)(VIN – VIN_L + VOS) + 0.3V

VREF = VSS = 0V

where the new VIN end points are:

EQUATION 1-9:

VIN_L

=

0---.--3---V------–----V----R---E---F--

G

+

VRE

F

VIN_H

=

-V---D----D-----–-----0---.-3---V------–----V----R---E---F--

G

+

V

REF

The equations for extracting the specifications do not

change.

V4

0

V3

0.3

0G

VIN (V)

VDD – 0.3 VDD

GG

FIGURE 1-7:

Output Voltage INL with the

standard condition VREF = VSS = 0 V.

 2004 Microchip Technology Inc.

DS21908A-page 9

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