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SI8610BC-B-IS 데이터 시트보기 (PDF) - Silicon Laboratories

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SI8610BC-B-IS
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SI8610BC-B-IS Datasheet PDF : 36 Pages
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Si8610/20/21/22
Table 3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
VDD Undervoltage Threshold
VDDUV+ VDD1, VDD2 rising
1.95
VDD Undervoltage Threshold
VDDUV– VDD1, VDD2 falling
1.88
VDD Negative-Going Lockout
VDDHYS
50
Hysteresis
2.24
2.375
V
2.16
2.325
V
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance1
VHYS
0.38
VIH
2.0
VIL
VOH
loh = –4 mA VDD1,VDD2 – 0.4
VOL
lol = 4 mA
IL
ZO
DC Supply Current (All inputs 0 V or at supply)
0.44
3.1
0.2
50
0.50
V
V
0.8
V
V
0.4
V
±10
µA
Si8610Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
0.6
1.2
0.8
1.5
mA
1.8
2.9
0.8
1.5
Si8620Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
0.8
1.4
1.4
2.2
mA
3.3
5.3
1.4
2.2
Si8621Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.2
1.9
1.2
1.9
mA
2.4
3.8
2.4
3.8
Si8622Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.6
4.2
3.3
5.3
mA
4.0
6.4
4.8
7.7
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.3

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