HD49343NP 데이터 시트보기 (PDF) - Renesas Electronics
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HD49343NP Datasheet PDF : 23 Pages
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HD49343NP/HNP
Preliminary
Explanation of Serial Data
PGA Gain (D4 to D13 of address 0)
Refer to the P.4 block diagram for details. A gain shifts 3 dB by voltage setup (D12 of address 4) of VRT.
PGA gain: –6dB + 0.04 dB N (Log linear)
1V
4095
1.4 V
4095
1.4 V
2.0 V
CDS
PGA
ADC
CDS
PGA
ADC
(CDS is –6 dB)
0.04 dB × N
(1) At VRT = 2.0 V settings (CDS input range is 1.4 Vp-p)
(CDS is –6 dB)
0.04 dB × N
(2) At VRT = 2.4 V settings (CDS input range is 2.0 Vp-p)
Figure 3 Level Dia of PGA
Gain (dB)
40
30
34dB
31dB
20
(At VRT = 2.0V)
10
0
–6dB
–9dB –10
0
(At VRT = 2.4V)
128 256 384 512 640 768 896 1023 (PGA gain code)
Figure 4 PGA Gain Characteristics
LPF_sel (D4 to D6 of address 1)
Frequency band restrictions of a CDS input part are chosen.
LPF_sel
0
1
2
3
4
5
6
7
Sensor Frequency
6 MHz
12 MHz
18 MHz
25 MHz
30 MHz
35 MHz
40 MHz
50 MHz
Although S/N will rise if a frequency band is lowered, but opposite side amplifier
operation becomes slow and which problem with line crawl and insufficient gain
occurs. Please choose a high point from the actually used frequency.
About LFP_sel, followings are only testing guaranteed.
(1) At Low Power mode: Data = 3
(2) At Normal Power mode: Data = 6
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 9 of 22
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