T35L6432B 데이터 시트보기 (PDF) - Taiwan Memory Technology

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T35L6432B

64K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

T35L6432B

PIN DESCRIPTIONS (continued)

QFP PINS

85

SYM.

ADSC

TYPE

DESCRIPTION

Address Status Controller:This active LOW input causes

Input- device to be deselected or selected along with new external

Synchronous address to be registered. A READ or WRITE cycle is

initiated depending upon write control inputs.

Mode: This input selects the burst sequence. A LOW on this

Input- pin selects LINEAR BURST. A NC or HIGH on this pin

31

MODE

Static selects INTERLEAVED BURST. Do not alter input state

while device is operating.

Snooze Enable: This active HIGH asynchronous input causes

64

ZZ

Input the device to enter a low-power standby mode in which all

data in the memory arry is retained.

2, 3, 6-9, 12, 13,

18, 19, 22-25,

28, 29, 52, 53,

56-59, 62, 63,

68, 69, 72-75,

78, 79,

DQ1-

DQ32

Input/

Output

Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is

DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-

DQ32. Input data must meet setup and hold times around the

rising edge of CLK.

15,41,65,91

17,40,67,90

4,11,20,27,54,

61,70,77

5,10,21,26,55,

60,71,76

VCC

VSS

VCCQ

VSSQ

Supply

Ground

Power Supply: 3.3V (+0.3V/-0.165V)

Ground: GND

I/O Supply Output Buffer Supply: 3.3V (+0.3V/-0.165V)

I/O Ground Output Buffer Ground: GND

1,14,16,30,38,

39,42,43,50,51, NC

66,80

-

No Connect: These signals are not internally conntected.

Taiwan Memory Technology, Inc. reserves the right P. 5

to change products or specifications without notice.

Publication Date: JUL. 2002

Revision: A

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