ML60851D 데이터 시트보기 (PDF) - Oki Electric Industry
부품명
상세내역
제조사
ML60851D Datasheet PDF : 82 Pages
| |||
1Semiconductor
PEDL60851D-01
ML60851D
End Point 2 Transmit FIFO (EP2TXFIFO)
Read address
—
Write address
C2h
D7 D6 D5 D4 D3 D2 D1 D0
After a hardware reset x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP2 Transmit data (W)
The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851D
issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be
invalid.
The EP2 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP2.
2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).
End Point 3 Transmit FIFO (EP3TXFIFO)
Read address
—
Write address
C3h
D7 D6 D5 D4 D3 D2 D1 D0
After a hardware reset x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP3 Transmit data (W)
The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data
in EP3TXFIFO when the ML60851D issues an EP3 packet ready interrupt request. It is possible to write the
packet data successively by writing continuously.
The EP3 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP3.
2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).
10/82
Share Link: 