1Semiconductor
PEDL60851D-01
ML60851D
INTERNAL REGISTERS
Addresses and Names of Registers
Addresses
A5:A0
Read
A7, A6
Write
A7, A6
00h
01b
—
01h
01b
—
02h
01b
—
03h
01b
—
00h
—
11b
01h
—
11b
02h
—
11b
03h
—
11b
Symbol
EP0RXFIFO
EP1RXFIFO
EP2RXFIFO
EP0TXFIFO
EP1TXFIFO
EP2TXFIFO
EP3TXFIFO
Register
Register name
Endpoint 0 Receive FIFO Data
Endpoint 1 Receive FIFO Data
Endpoint 2 Receive FIFO Data
Reserved
Endpoint 0 Transmit FIFO Data
Endpoint 1 Transmit FIFO Data
Endpoint 2 Transmit FIFO Data
Endpoint 3 Transmit FIFO Data
00h
11b
01b DVCADR
Device Address Register
01h
11b
01b DVCSTAT
Device Status Register
02h
11b
— PKTERR
Packet Error Register
03h
11b
— FIFOSTAT1
FIFO Status Register 1
04h
11b
— FIFOSTAT2
FIFO Status Register 2
08h
11b
01b PKTRDY
Endpoint Packet-Ready Register
09h
11b
— EP0RXCNT
Endpoint 0 Receive-Byte Count Register
0Ah
11b
— EP1RXCNT
Endpoint 1 Receive-Byte Count Register
0Bh
11b
— EP2RXCNT
Endpoint 2 Receive-Byte Count Register
0Ch
11b
—
Reserved
0Dh
11b
— REVISION
Revision Register
0Eh
—
01b CLRFIFO
Transmit FIFO Clear Register
0Fh
—
01b SYSCON
System Control Register
10h
11b
— BmRequest Type BmRequest Type Setup Register
11h
11b
— bRequest
bRequest Setup Register
12h
11b
— WValue LSB
WValue LSB Setup Register
13h
11b
— WValue MSB
WValue MSB Setup Register
14h
11b
— WIndex LSB
WIndex LSB Setup Register
15h
11b
— WIndex MSB
WIndex MSB Setup Register
16h
11b
— WLength LSB
WLength LSB Setup Register
17h
11b
— WLength MSB
WLength MSB Setup Register
1Ah
11b
01b POLSEL
Assertion Select Register
1Bh
11b
01b INTENBL
Interrupt Enable Register
1Ch
11b
— INTSTAT
Interrupt Status Register
1Dh
11b
01b DMACON
DMA Control Register
1Eh
11b
01b DMAINTVL
DMA Interval Register
1Fh
—
—
Reserved
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