ML60851DGA 데이터 시트보기 (PDF) - Oki Electric Industry
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ML60851DGA Datasheet PDF : 82 Pages
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1Semiconductor
PEDL60851D-01
ML60851D
End Point 2 Receive FIFO (EP2RXFIFO)
Read address
42h
Write address
—
D7 D6 D5 D4 D3 D2 D1 D0
After a hardware reset x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP2 Receive data (R)
It is possible to read out the EP2 receive data by reading the address 42h. When EP2 is set for bulk reception (Bulk
OUT), the local MCU should read EP2RXFIFO when the ML60851D issues an EP2 packet ready interrupt request.
It is possible to read successively the data in the packet by reading continuously. When the data transfer direction
of EP2 is set as ‘Transmit’, all accesses to this address will be invalid.
The EP2RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP2.
2. When the EP2 receive packet ready bit is reset. (A “1” is written in PKTRDY(2).)
3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).
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