ML60852A 데이터 시트보기 (PDF) - Oki Electric Industry
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ML60852A Datasheet PDF : 81 Pages
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1Semiconductor
FEDL60852A-03
ML60852A
Application Interface
Signal
D15: D8
AD7: AD0
A6: A0
CS
RD
WR
INTR
DREQ0
DREQ1
DACK0
DACK1
ALE/PUCTL
ADSEL
RESET
Type
I/O
I/O
I
I
I
I
O
O
O
I
I
I or O
I
I
Assertion
—
—
—
LOW
LOW
LOW
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
HIGH
—
LOW
Description
Upper byte (MSB) of data bus.
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW.
Chip Select. When this signal is asserted LOW, the ML60852A is selected
and ready to read or write data. This signal is invalid in single address
mode during DMA transfer.
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
Interrupt Request. When this signal is asserted, the ML60852A makes an
interrupt request to the application.
DMA Request. This signal requests the DMA0 to make a DMA transfer.
DMA Request. This signal requests the DMA1 to make a DMA transfer.
DMA Acknowledge Signal for DREQ0. This signal, when asserted, enables
accessing FIFOs, without address bus setting.
DMA Acknowledge Signal for DREQ1. This signal, when asserted, enables
accessing FIFO, without address bus setting.
When ADSEL is HIGH, the address and CS on AD7: AD0 are latched at the
trailing edge of this signal. D+ pull-up resistor connection output when
ADSEL is LOW.
VCC potential when bit D3 of SYSCON register is “1”, and high-impedance
when it is “0”.
When ADSEL is LOW, the address is input on A6: A0 and data is input on
AD7: AD0. When ADSEL is HIGH, address and data are multiplexed on
AD7: AD0.
System Reset. When this signal is asserted LOW, the ML60852A is reset.
When the ML60852A is powered on, this signal must be asserted for 1 µs
or more.
Notes: 1. The assertion polarity can be modified by appropriately initializing the polarity selection
register (POLSEL).
The default is LOW.
2. The assertion polarity can be modified by appropriately initializing the polarity selection
register (POLSEL).
The default is HIGH.
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