LTC1550 데이터 시트보기 (PDF) - Linear Technology
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LTC1550 Datasheet PDF : 12 Pages
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LTC1550/LTC1551
TYPICAL PERFORMANCE CHARACTERISTICS
Spot Noise
(See Figure 2, COUT = 10µF)
10
VCC = 5V
IL = 5mA
CIN = 4.7µF
COUT = 10µF
1
CL = 0.1µF
0.1
0.01
1
10
FREQUENCY (kHz)
100
LTC1550/51 • G12
Output Spectrum
(See Figure 2, COUT = 22µF)
90
80
VCC = 5V
IL = 5mA
70 CIN 4.7µF
COUT = 22µF
60 CL = 0.1µF
50
40
30
20
10
0
–10
100k
1M
10M
FREQUENCY (Hz)
LT1550/51 • G13
Spot Noise
(See Figure 2, COUT = 22µF)
10
VCC = 5V
IL = 5mA
CIN = 4.7µF
COUT = 22µF
1
CL = 0.1µF
0.1
0.01
1
10
FREQUENCY (kHz)
100
LTC1550/51 • G14
PIN FUNCTIONS
SHDN: Shutdown (TTL Compatible). This pin is active low
(SHDN) for the LTC1550 and active high (SHDN) for the
LTC1551. When this pin is at VCC (GND for LTC1551), the
LTC1550 operates normally. When SHDN is pulled low
(high for LTC1551), the LTC1550 enters shutdown mode.
In shutdown, the charge pump stops, the output collapses
to 0V, and the quiescent current drops typically to 0.2µA.
VCC: Power Supply. VCC requires an input voltage between
4.5V and 6.5V for the fixed voltage LTC1550CS8-4.1/
LTC1551CS8-4.1. The adjustable voltage LTC1550CGN/
LTC1550IGN operates with a VCC range of 2.7V to 6.5V.
Output voltage and output load current conditions depend
on the VCC supply voltage. Consult the Electrical Charac-
teristics table and Typical Performance Characteristics for
guaranteed test points. The difference between the input
voltage and output should never be set to exceed 14V or
damage to the chip may occur. VCC must be bypassed to
PGND (GND for 8-pin packages) with at least a 0.1µF
capacitor placed in close proximity to the chip. A 4.7µF or
larger bypass capacitor is recommended to minimize
noise and ripple at the output.
C1+: C1 Positive Input. Connect a 0.1µF capacitor between
C1+ and C1–.
VOUT: Negative Voltage Output. This pin must be bypassed
to ground with a 4.7µF or larger capacitor to ensure
regulator loop stability. At least 10µF is recommended to
provide specified output ripple. An additional 0.1µF low
ESR capacitor is recommended to minimize high fre-
quency spikes at the output.
C1–: C1 Negative Input. Connect a 0.1µF capacitor from
C1+ to C1–.
GND: Ground. Connect to a low impedance ground. A
ground plane will help minimize regulation errors.
CPOUT: Negative Charge Pump Output. This pin requires a
0.1µF storage capacitor to ground.
SENSE: Connect to VOUT. The LTC1550/LTC1551 internal
regulator uses this pin to sense the output voltage. For
optimum regulation, SENSE should be connected close to
the output load.
SSOP PACKAGE ONLY
PGND: Power Ground. Connect to a low impedance ground.
PGND should be connected to the same potential as
AGND.
AGND: Analog Ground. Connect to a low impedance
ground. AGND should be connected to a ground plane to
minimize regulation errors.
5
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