M25P64-VMF6G 데이터 시트보기 (PDF) - STMicroelectronics

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M25P64-VMF6G

64 Mbit, low voltage, Serial Flash memory with 50 MHz SPI bus interface

STMicroelectronics 

M25P64

Figure 1. Logic diagram

VCC

D

C

S

W/VPP

HOLD

Q

M25P64

Description

VSS

AI07485B

Table 1. Signal names

Signal name

Function

C

D

Q

S

W/VPP

HOLD

VCC

VSS

Serial Clock

Serial Data Input

Serial Data Output

Chip Select

Write Protect/Enhanced Program Supply Voltage

Hold

Supply Voltage

Ground

Figure 2. VDFPN connections

M25P64

Direction

Input

Input

Output

Input

Input

Input

S1

Q2

W/VPP 3

VSS 4

8 VCC

7 HOLD

6C

5D

AI08595B

1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally, to VSS,

and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.

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