PLUS405-37A 데이터 시트보기 (PDF) - Philips Electronics
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PLUS405-37A Datasheet PDF : 20 Pages
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Philips Semiconductors
Programmable logic sequencers
(16 × 64 × 8)
Product specification
PLUS405-37/-45
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic DIP (600mil-wide)
28-Pin Plastic DIP (600mil-wide)
28-Pin Plastic Leaded Chip Carrier
28-Pin Plastic Leaded Chip Carrier
OPERATING
FREQUENCY
45MHz (tIS1 + tCKO1)
37MHz (tIS1 + tCKO1)
45MHz (tIS1 + tCKO1)
37MHz (tIS1 + tCKO1)
ORDER CODE
PLUS405–45N
PLUS405–37N
PLUS405–45A
PLUS405–37A
DRAWING NUMBER
SOT117-2
SOT117-2
SOT261-3
SOT261-3
PIN DESCRIPTION
PIN NO. SYMBOL
1
CLK1
2, 3, 5–9,
26–27
20–22
4
I0–I4, I7, I6
I8–I9
I13–I15
CLK2
23
I12
24
I11
25
I10
10–13
15–18
F0 – F7
19
INIT/OE
NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this
line is necessary to update the contents of both state and output registers. Pin 1 only
clocks P0–3 and F0–3 if Pin 4 is also being used as a clock.
Logic Inputs: The 12 external inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence. True and complement
signals are generated via use of “H” and “L”.
Logic Input/Clock: A user programmable function:
• Logic Input: A 13th external logic input to the AND array, as above.
• Clock: A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above.
Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t
Care”) when using Pin 4 as a Clock.
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when
exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0–F7
reflect the contents of State Register bits P0–P7. The contents of each Output Register
remains unaltered.
Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when
exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become
direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents
of each Output Register remains unaltered.
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when
exercising standard TTL levels. When I10 is held at +10V, device outputs F0–F7 become
direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The con-
tents of each State Register remains unaltered.
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which nor-
mally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is held
at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State Reg-
ister bits P0–P7. When I10 is held at +10V, F0–F7 become inputs to Output Register bits
Q0–Q7.
Initialization or Output Enable Input: A user programmable function:
• Initialization: Provides an asynchronous preset to logic “1” or reset to logic “0” of all
State and Output Register bits, determined individually for each register bit through user
programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7
and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock
pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for
tNVCK and tVCK.
• Output Enable: Provides an output enable function to buffers F0–F7 from the Output
Registers.
POLARITY
Active-High (H)
Active-High/Low
(H/L)
Active-High/Low
(H/L)
Active-High (H)
Active-High/Low
(H/L)
Active-High/Low
(H/L)
Active-High/Low
(H/L)
Active-High (H)
Active-High (H)
Active-Low (L)
1996 Nov 12
3
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