AD9814 데이터 시트보기 (PDF) - Analog Devices
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AD9814 Datasheet PDF : 15 Pages
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AD9814
NOTES
1The Integral Nonlinearity in measured using the “fixed endpoint” method, NOT using a “best-fit” calculation. See Definitions of Specifications.
2The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
3Linear input signal range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9814’s input clamp. A larger reset transient can be tolerated
by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
4The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device.
Signals beyond the input limits will turn on the overvoltage protection diodes.
5The PGA Gain is approximately “linear in dB” and follows the equation: Gain = [
5.8
] where G is the register value. See Figure 13.
63 – G
1 + 4.8 [
]
Specifications subject to change without notice.
63
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 = 2 MHz,
CL = 10 pF, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
VIH
2.6
Low Level Input Voltage
VIL
High Level Input Current
IIH
10
Low Level Input Current
IIL
10
Input Capacitance
CIN
10
LOGIC OUTPUTS
High Level Output Voltage
VOH
4.5
Low Level Output Voltage
VOL
High Level Output Current
IOH
50
Low Level Output Current
IOL
50
Specifications subject to change without notice.
V
0.8
V
µA
µA
pF
V
0.1
V
µA
µA
TIMING SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V)
Parameter
Symbol
Min
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
tPRA
300
tPRB
140
tADCLK
45
tC1
20
CDSCLK2 Pulsewidth
tC2
40
CDSCLK1 Falling to CDSCLK2 Rising
tC1C2
0
ADCCLK Falling to CDSCLK2 Rising
tADC2
10
CDSCLK2 Rising to ADCCLK Rising
tC2ADR
10
CDSCLK2 Falling to ADCCLK Falling
tC2ADF
50
CDSCLK2 Falling to CDSCLK1 Rising
tC2C1
50
ADCCLK Falling to CDSCLK1 Rising
tADC1
0
Aperture Delay for CDS Clocks
tAD
SERIAL INTERFACE
Maximum SCLK Frequency
fSCLK
10
SLOAD to SCLK Set-Up Time
tLS
10
SCLK to SLOAD Hold Time
tLH
10
SDATA to SCLK Rising Set-Up Time
tDS
10
SCLK Rising to SDATA Hold Time
tDH
10
SCLK Falling to SDATA Valid
tRDV
10
DATA OUTPUT
Output Delay
tOD
3-State to Data Valid
tDV
Output Enable High to 3-State
tHZ
Latency (Pipeline Delay)
Specifications subject to change without notice.
REV. 0
–3–
Typ
Max
500
3
6
16
5
3 (Fixed)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
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