88ALP01 데이터 시트보기 (PDF) - Marvell Semiconductor

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88ALP01

PCI to NAND, SD and Camera Host Controller

Marvell Semiconductor 

List of Tables

List of Tables

1 Signal Description ............................................................................................................................ 21

1.1

Signal Diagram................................................................................................................................................21

1.2

128-Pin TQFP Package ..................................................................................................................................22

1.3

Pin Description ................................................................................................................................................23

Table 1: Pin Type Definitions ..........................................................................................................................23

Table 2: SD/SDIO Interface (3.3V) .................................................................................................................23

Table 3: PCI Interface (3.3V) ..........................................................................................................................24

Table 4: NAND Flash (3.3V) ...........................................................................................................................25

Table 5: Camera Interface (2.5 or 3.3V) .........................................................................................................26

Table 6: VPD TWSI (Serial EEPROM, 3.3V) ..................................................................................................26

Table 7: Main Clock Interface (PLL, 3.3V) ......................................................................................................27

Table 8: GPIO Interface (3.3V) .......................................................................................................................27

Table 9: Joint Test Action Group (JTAG) and Test Interface (3.3V) ...............................................................27

Table 10: Core VDD Control (1.2V) ..................................................................................................................28

Table 11: Power and Ground............................................................................................................................28

2 Functional Description..................................................................................................................... 29

2.1

System Overview ............................................................................................................................................29

2.2

Functional Overview........................................................................................................................................30

Table 12: Samsung Type 1 NAND Flash Device Command Sets and Support ...............................................35

Table 13: Samsung Type 2 NAND Flash Device Command Sets and Support ...............................................35

Table 14: CCIC Chip-Level I/O Signal Descriptions (2.5V or 3.3V) ..................................................................45

Table 15: Supported Interface Modes ..............................................................................................................46

Table 16: Color I/O Matrix.................................................................................................................................47

Table 17: Video Timing Reference Codes ........................................................................................................47

Table 18: Bits States ........................................................................................................................................47

Table 19: 8-bit RGB 5:6:5 Input Data Format ...................................................................................................48

Table 20: 8-bit YCbCr 4:2:2 Input Data Format ................................................................................................48

Table 21: Data Format of First 8 byte Block within Serial EEPROM ................................................................51

Table 22: 88ALP01 Configuration Pins.............................................................................................................52

Table 23: Device Power Status ........................................................................................................................53

3 Register Description......................................................................................................................... 55

3.1

Registers Introduction .....................................................................................................................................55

Table 24: Register Type Definitions..................................................................................................................55

3.2

PCI Configuration Register File.......................................................................................................................56

Table 25: PCI Header Region Overview...........................................................................................................57

Table 26: PCI Header Region Register Map ....................................................................................................58

Table 55: Power Management Data Table .......................................................................................................74

3.3

Global Control Registers .................................................................................................................................81

Copyright © 2007 Marvell

July 17, 2007, Preliminary

Document Classification: Proprietary Information

Doc. No. MV-S103921-00 Rev. –

Page 9

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