MC68LC302PU16V 데이터 시트보기 (PDF) - Motorola => Freescale

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MC68LC302PU16V

Low Power Integrated Multiprotocol Processor Reference Manual

Motorola => Freescale 

Introduction

1.2 FEATURES

The features of the LC302 are as follows. The items in bold face type show major differenc-

es from the MC68302, although a complete list of differences is given in 1.4 LC302 Differ-

ences.

• On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family-System

• SIB Including:

Independent Direct Memory Access (IDMA) Controller.

Interrupt Controller with Two Modes of Operation

Parallel Input/Output (I/O) Ports, some with Interrupt Capability

Parallel Input/Output (I/O) Ports on D15-D8 in 8 bit mode

On-Chip 1152-Byte Dual-Port RAM

Three Timers Including a Watchdog Timer

New Periodic Interrupt Timer (PIT)

Four Programmable Chip-Select Lines with Wait-State Generator Logic

Programmable Address Mapping of the Dual-Port RAM and IMP Registers

On-Chip Clock Generator with Output Signal

On-Chip PLL Allows Operation with 32kHz or 4MHz Crystals

Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM

Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode

System Control:

System Status and Control Logic

Disable CPU Logic (Slave Mode Operation)

Hardware Watchdog

New Low-Power (Standby) Modes With Wake-up From 2 Pins or PIT

Freeze Control for Debugging (Available Only in the PGA Package)

DRAM Refresh Controller

• CP Including:

Main Controller (RISC Processor)

Two Independent Full-Duplex Serial Communications Controllers (SCCs)

Supporting Various Protocols:

High-Level/Synchronous Data Link Control (HDLC/SDLC)

Universal Asynchronous Receiver Transmitter (UART)

Binary Synchronous Communication (BISYNC)

Transparent Modes

Autobaud Support Instead of DDCMP and V.110

Boot from SCC Capability

1-2

MC68LC302 REFERENCE MANUAL

MOTOROLA

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