3291-04 데이터 시트보기 (PDF) - Peregrine Semiconductor
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3291-04
Peregrine Semiconductor
3291-04 Datasheet PDF : 20 Pages
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PE3291
Product Specification
Table 7. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Control Interface and Latches (see figure 8)
fClk
Serial data clock frequency
tClockH
Serial clock HIGH time
tClockL
Serial clock LOW time
tDSU
Data set-up time to Clock rising edge
tDHLD
Data hold time after Clock rising edge
tLEW
LE pulse width
tCLE
Clock falling edge to LE rising edge
tLEC
LE falling edge to Clock rising edge
tData Out
Data Out delay after Clock falling edge (foLD pin)
Main Divider (Including Prescaler)
fin1
Operating frequency (see figure 6)
fin2
Operating frequency (see figure 6)
Pfin1
Input level range
Pfin2
Input level range
fc
Comparison frequency
Reference Divider
fr
Operating frequency
Vfr
Input sensitivity
Note 1: CMOS logic levels may be used if DC coupled.
Conditions
CL = 50 pf
P2, P1 = 00
VDD1 = 1.0 volts
VDD1 = 1.8 volts
VDD1 = 2.7 volts
P2, P1 = 01
VDD1 = internally generated (low speed)
P2, P1 = 1X = (10 or 11)
VDD1 = internally generated (high speed)
P2, P1 = 00
VDD1 = 1.0 volts
VDD1 = 1.8 volts
VDD1 = 2.7 volts
P2, P1 = 01 or 10
VDD2 = internally generated (low speed)
P2, P1 = 11
VDD1 = internally generated (high speed)
External AC coupling
External AC coupling
External AC coupling (note 1)
Min
Max Units
10
MHz
50
ns
50
ns
50
ns
10
ns
50
ns
50
ns
50
ns
90
ns
300
450
MHz
300
900
MHz
300
1200
MHz
300
800
MHz
300
1100
MHz
45
300
MHz
45
550
MHz
45
550
MHz
45
300
MHz
45
550
MHz
-10
5
MHz
-10
5
dBm
10
MHz
50
MHz
0.5
VP-P
Copyright Peregrine Semiconductor Corp. 2001
Page 8 of 20
File No. 70/0009~03C | UTSi CMOS RFIC SOLUTIONS
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