DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

TS555C 데이터 시트보기 (PDF) - STMicroelectronics

부품명
상세내역
제조사
TS555C
ST-Microelectronics
STMicroelectronics ST-Microelectronics
TS555C Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TS555C,I,M
TYPICAL CHARACTERISTICS
Figure 1 : Supply Current (each timer) versus
Supply Voltage
300
200
100
0
4
8
12
16
SUPPLY VOLTAGE, VCC (V)
APPLICATION INFORMATION
MONOSTABLE OPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure 2 the external capaci-
tor is initially held discharged by a transistor inside
the timer.
Figure 2
The circuit triggers on a negative-goinginput signal
when the level reaches 1/3 VCC. Once triggered,the
circuit remains in this state until the set time has
elapsed,even if it is triggered again during this
interval. The duration of the output HIGH state is
given by t = 1.1 R x C.
Notice that since the charge rate and the threshold
level of the comparator are both directly propor-
tional to supply voltage, the timing interval is inde-
pendent of supply. Applying a negative pulse
simultaneouslyto the Reset terminal (pin 4) and the
Trigger terminal (pin 2) during the timing cycle
discharges the external capacitor and causes the
cycle to start over. The timing cycle now starts on
the positive edge of the reset pulse. During the time
the reset pulse is applied, the output is driven to its
LOW state.
When a negative trigger pulse is applied to pin 2,
the flip-flop is set, releasing the short circuit across
the external capacitor and driving the output HIGH.
The voltage across the capacitor increases expo-
nentially with the time constant τ = R x C.
When the voltage across the capacitor equals 2/3
VCC, the comparator resets the flip-flop which then
discharges the capacitor rapidly and drives the
output to its LOW state.
Figure 3 shows the actual waveforms generated in
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.
VCC
Reset
R
4
8
Trigger
2
7
TS555 6
C
Figure 3
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
Out
3
5
Control Voltage
1
0.01µF
CAPACITOR VOLTAGE = 2.0V/div
R = 9.1k, C = 0.01µ F , RL = 1.0k
8/12

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]