5L35023 데이터 시트보기 (PDF) - Integrated Device Technology

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5L35023

VersaClock® 3S Programmable Clock Generator

Integrated Device Technology 

5L35023 Datasheet

Table 1. Pin Descriptions (Cont.)

Number

14

Name

SE1

Type

Output

15

OE1

Input

16

VDDDIFF1

Power

17

DIFF1B

Output

18

DIFF1

Output

19

SE3

Output

20

VDDSE3

Power

21

OE3

Input

22

VDDDIFF2

Power

23

DIFF2B

Output

24

DIFF2

Output

EPAD

Power

Description

Output clock SE1.

OE1 function selected from OTP pre-program register bits.

OE1 pull to 6.5V when burn OTP registers.

Refer to OE function table for details.

Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1.

Differential clock output 1_Complement; can be OTP pre-programmed to

LVCMOS/LPHCSL output type.

Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL

output type.

Output clock SE3.

Output power supply. Connect to 1.8V. Sets output voltage levels for SE3.

Output enable control 3, multi-function pin. Refer to OE Pin Function table.

Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2.

Differential clock output 2_Complement; can be OTP pre-programmed to

LVCMOS/LPHCSL output type.

Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL

output type.

Connect to ground pad.

Detailed Block Diagram

CLKINB/X1

CLKIN/X2

VBAT

VDD18

VDDA

VSS

SCL_DFC 1

SDA_DFC0

OSC

Power

Monitor

POR

Calibration

32.768K

DCO

PLL1

MUX

PLL2

MUX

PLL3

MUX

DIV

1

DIV

2

MUX

DIV

3

MUX

DIV

4

DIV

5

DIV1 /REF

DIV3

MUX

DIV1 /REF

DIV3

MUX

DIV2

DIV4 /REF

32K

MUX

DIV4/REF

DIV5

32K

MUX

DIV4 /REF

DIV5

32K

MUX

I2C Engine

Overshot Reduction

(ORT)

Dynamic Frequency Control Logic (DFC)

OTP memory (1 configuration)

Proactive Power Saving Logic (PPS)

Timer

VDDDIFF2

DIFF2

DIFF2B

VDDDIFF1

DIFF1

DIFF1B

OE3

SE3

VDDSE3

OE2

SE2

VDDSE2

OE1

SE1

VDDSE1

REF

©2017 Integrated Device Technology, Inc.

3

July 13, 2017

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