5L35023 데이터 시트보기 (PDF) - Integrated Device Technology
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5L35023 Datasheet PDF : 38 Pages
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5L35023 Datasheet
Electrical Characteristics
Supply voltage: all VDD ±5%, unless stated otherwise
Table 6. Electrical Characteristics – Current Consumption 1,2
Symbol
IDDCORE
IDD_PLL1 3
IDD_PLL2 3
IDD_PLL3 3
IDDOx
IDDPD 3
IDDPD 3,6
IDDUPD 4
IDDUPD 4
IDDSUSPEND 5
IDDSUSPEND 5
IDDSUSPEND 5
Parameter
Conditions
Core Supply Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL2/3 off, no output, PLLs disabled.
PLL1 Supply
Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL2/3 off, no output, PLL1 = 600MHz.
PLL2 Supply
Current
PLL3 Supply
Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL1/3 off, no output, PLL2 = 60MHz.
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL1/2 off, no output, PLL3 = 480MHz.
Output Buffer
Supply Current
Power Down
Current–LPHCSL
Power Down
Current–LVCMOS
Ultra Power Down
Current–LPHCSL
Ultra Power Down
Current–LVCMOS
Suspend Mode
Current–32kHz x 1
Suspend Mode
Current–32kHz x 2
Suspend Mode
Current–32kHz x 3
LPHCSL, 125MHz, 1.8V VDDDIFF, no load
(DIFF1,2).
LPHCSL, 100MHz, 1.8V VDDDIFF, no load
(DIFF1,2).
LVCMOS, 8MHz, 1.8V, VDDSE 1,2 (SE1).
LVCMOS, 160MHz, 1.8V VDDSEx 1,2 (SE1).
I2C functional during power-down, just 32kHz
running (if any); DIFF outputs in LPHCSL mode
are high/low.
I2C functional during power-down, just 32kHz
running (if any); DIFF outputs in LVCMOS mode
are high/low or low/low.
I2C functional during power-down, just 32kHz
running (if any); DIFF outputs in LPHCSL mode
are low/low.
I2C functional during power-down, just 32kHz
running (if any) – DIFF outputs in LVCMOS mode
are low/low.
I2C off in Suspend Mode. One 32kHz output
running.
I2C off in Suspend Mode. Two 32kHz outputs
running.
I2C off in Suspend Mode. Three 32kHz outputs
running.
Minimum
Typical
3.4
12.1
0.5
2.5
3.4
2.9
0.5
2.7
2.6
0.5
33
33
1.4
3.2
3.7
Maximum
4.8
15.3
0.8
3.2
4.1
3.5
0.6
3.4
3.4
1
65
65
2.1
7.9
8.6
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
1 All output currents measured with 0.5 inch transmission line and 0pF load.
2 Single CMOS driver active.
3 Power-down can be controlled by PD (OE1 input pin) and/or I2C bit.
4 Ultra power-down must be controlled by PD (OE1 input pin).
5 Suspend Mode requires all VDD to GND except VDDSEn (as desired) and VDD18.
6 DIFF outputs in LVCMOS mode can power-down to be high/low or low/low, depending on register 0x22<1:0>.
©2017 Integrated Device Technology, Inc.
6
July 13, 2017
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