IDT9FGV0641 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT9FGV0641

6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator with Zo=100ohms

Integrated Device Technology 

9FGV0641 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a stop bit

Index Block Write Operation

Controller (Host)

IDT (Slave/Receiver)

T

starT bit

Slave Address

WR

WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

ACK

O

O

O

O

O

O

Byte N + X - 1

ACK

P

stoP bit

Note: SMBus address is latched on SADR pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X(H) was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Controller (Host)

IDT (Slave/Receiver)

T

starT bit

Slave Address

WR

WRite

ACK

Beginning Byte = N

ACK

RT

Repeat starT

Slave Address

RD

ReaD

ACK

ACK

ACK

O

O

O

N

Not acknowledge

P

stoP bit

Data Byte Count=X

Beginning Byte N

O

O

O

Byte N + X - 1

JUNE 23, 2017

9

6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR WITH ZO=100OHMS

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