FH8065403552500SR3GQ 데이터 시트보기 (PDF) - Intel
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FH8065403552500SR3GQ Datasheet PDF : 745 Pages
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Contents—C2000 Product Family
4.7
4.8
4.9
4.10
4.11
4.12
4.6.2 Fatal Errors .......................................................................................... 69
4.6.3 Non-Fatal Errors ................................................................................... 69
4.6.3.1 Software Correctable Errors ................................................... 69
Global Error Reporting ....................................................................................... 70
4.7.1 Reporting Errors to CPU ......................................................................... 72
4.7.1.1 Non-Maskable Interrupt (NMI) ............................................... 72
4.7.1.2 System Management Interrupt (SMI) ...................................... 72
4.7.2 Reporting Global Errors to an External Device ........................................... 72
4.7.3 Machine Check Architecture.................................................................... 72
4.7.3.1 Machine Check Availability and Discovery ................................ 75
4.7.3.2 P5 Compatibility MSRs .......................................................... 75
4.7.3.3 Machine Check Global Control MSRs........................................ 76
4.7.3.4 Machine Check Error-Reporting MSR Banks 0-5 ........................ 77
4.7.4 Error-Status Cloaking Feature................................................................. 88
4.7.4.1 Hide Corrected-Error Status From OS...................................... 88
4.7.4.2 SMI for MCA Uncorrected Errors ............................................. 88
4.7.5 MCERR/IERR Signaling........................................................................... 89
4.7.6 PCI Express INTx and MSI...................................................................... 89
4.7.7 Error Register Overview ......................................................................... 90
4.7.7.1 Local Error Registers............................................................. 91
4.7.7.2 Global Error Registers ........................................................... 93
4.7.7.3 System Error (SERR) ............................................................ 95
4.7.7.4 First and Next Error Log Registers .......................................... 95
4.7.7.5 Error Register Flow ............................................................... 96
4.7.7.6 Error Counters ..................................................................... 97
SoC Error Handling Summary.............................................................................. 98
Register Map .................................................................................................. 105
System Agent Register Map .............................................................................. 106
4.10.1 Registers in Configuration Space ........................................................... 106
RAS Register Map............................................................................................ 107
4.11.1 Registers in Configuration Space ........................................................... 107
Root Complex Event Collector (RCEC) Register Map ............................................. 109
4.12.1 Registers in Configuration Space ........................................................... 109
5 Clock Architecture.................................................................................................. 111
5.1 Input Clocks ................................................................................................... 113
5.2 Output Clocks ................................................................................................. 114
6 Interrupt Architecture............................................................................................ 115
6.1 PCI Interrupts and Routing ............................................................................... 115
6.2 Non-Maskable Interrupt (NMI) .......................................................................... 118
6.3 System Management Interrupt (SMI) ................................................................. 118
6.4 System Control Interrupt (SCI) ......................................................................... 119
6.5 Message Signaled Interrupt (MSI and MSI-X) ...................................................... 119
6.6 I/O APIC Input Mapping ................................................................................... 120
6.7 8259 PIC Input Mapping................................................................................... 122
6.8 Device Interrupt-Generating Capabilities ............................................................ 123
7 SoC Reset and Power Supply Sequences ................................................................ 125
7.1 Power Up from G3 State (Mechanical Off) ........................................................... 125
7.1.1 While in the G3 State .......................................................................... 125
7.1.2 Powering-Up for the First Time ............................................................. 125
7.1.3 SUS Power Well Power-Up Sequence From the G3 State........................... 126
7.1.4 Core Power-Up Sequence ..................................................................... 129
7.2 Reset Sequences and Power-Down Sequences..................................................... 133
7.2.1 Cold Reset Sequence ........................................................................... 133
7.2.1.1 SUSPWRDNACK ................................................................. 138
January 2016
Order Number: 330061-003US
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
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