FH8065403552500SR3GQ 데이터 시트보기 (PDF) - Intel
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FH8065403552500SR3GQ Datasheet PDF : 745 Pages
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Contents—C2000 Product Family
9.12
9.11.1 Intel® Turbo Boost Technology ............................................................. 167
9.11.1.1 Voltage Regulator Constraints .............................................. 168
9.11.1.2 Thermal Design Power Constraints........................................ 168
9.11.2 Running Average Power Limiting (RAPL)................................................. 169
9.11.3 Always-On Timers (AONT).................................................................... 169
9.11.4 I/O Device Controller Enable/Disable ..................................................... 169
Voltage Identification (VID) Table ...................................................................... 169
10 System Address Maps ............................................................................................ 170
10.1 Physical Address Space Map ............................................................................. 170
10.1.1 SoC Transaction Router Memory Map..................................................... 171
10.1.1.1
10.1.1.2
10.1.1.3
10.1.1.4
Low MMIO ......................................................................... 173
DOS DRAM ........................................................................ 175
Additional Mappings............................................................ 176
Isolated Memory Regions .................................................... 176
10.1.2 I/O Fabric (MMIO) Map ........................................................................ 177
10.2 I/O Address Space........................................................................................... 180
10.2.1 SoC Transaction Router I/O Map ........................................................... 180
10.2.2 I/O Fabric I/O Map .............................................................................. 180
10.2.2.1 PCU Fixed I/O Address Ranges ............................................. 180
10.2.2.2 Variable I/O Address Ranges................................................ 182
10.3 PCI Configuration Space ................................................................................... 184
10.4 Sideband Registers .......................................................................................... 187
10.4.1 Sideband Register Access..................................................................... 187
10.4.1.1 Sideband Registers for Address Mapping................................ 188
11 Gigabit Ethernet (GbE) Controller .......................................................................... 189
11.1 Introduction ................................................................................................... 189
11.2 Programmer’s Reference Manual ....................................................................... 190
11.3 Feature List .................................................................................................... 190
11.4 Signal Descriptions .......................................................................................... 191
11.5 Architectural Overview ..................................................................................... 194
11.5.1 PCIe* Integrated Endpoint ................................................................... 195
11.5.2 Setting Up PCI Device Presence and Non-Presence .................................. 197
11.5.2.1 Soft Straps for GbE Controller .............................................. 197
11.5.3 Disabling LAN Ports and PCI Functions by EEPROM .................................. 198
11.5.4 Disabling PCI Functions by BIOS ........................................................... 198
11.5.5 Mapping PCI Functions to LAN Ports ...................................................... 198
11.5.6 LAN Port Interface .............................................................................. 199
11.5.7 Reference Clock Input ......................................................................... 201
11.5.8 Pin Straps .......................................................................................... 201
11.5.9 LED Interface ..................................................................................... 202
11.5.10 Software-Defined Pins ......................................................................... 203
11.5.11 SPI Interface ...................................................................................... 204
11.5.12 MDIO and I2C Interface ....................................................................... 204
11.5.12.1 Sharing the MDIO0 Interface ............................................... 205
11.5.13 SMBus and NC-SI Interface .................................................................. 207
11.5.13.1 SMBus 2.0......................................................................... 207
11.5.13.2 NC-SI and REF_CLK............................................................ 208
11.6 EEPROM ......................................................................................................... 209
11.6.1 EEPROM Starter Images....................................................................... 209
11.6.2 EEPROM Map...................................................................................... 211
11.6.3 Unique MAC Address ........................................................................... 214
11.6.4 Read EEPROM Contents ....................................................................... 214
11.6.5 Autoload from EEPROM and Resets........................................................ 214
11.6.6 VLAN Support..................................................................................... 214
January 2016
Order Number: 330061-003US
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
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