KSZ8765CLX 데이터 시트보기 (PDF) - Microchip Technology

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KSZ8765CLX

Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces

Microchip Technology 

KSZ8765CLX

1.0 INTRODUCTION

1.1 General Description

The KSZ8765CLX is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce

overall system cost. It is intended for cost-sensitive applications requiring four 10/100 Mbps copper ports and one 10/

100/1000 Mbps Gigabit uplink port. The KSZ8765CLX incorporates a small package outline, the lowest power consump-

tion with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management,

programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based

packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-per-

formance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8765CLX

provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and

Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the GMII, RGMII, MII, and RMII

modes.

The KSZ8765CLX is built upon industry-leading Ethernet analog and digital technology, with features designed to off-

load host processing and streamline the overall design.

• Two integrated MAC/PHYs 100BASE-FX on Port 1 and Port 2

• Two integrated MAC/PHYs 10/100BASE-T/TX on Port 3 and Port 4

• One integrated 10/100/1000BASE-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces

• Small 80-pin LQFP package

A robust assortment of power-management features including Energy Efficient Ethernet (EEE), power management

event (PME), and Wake-on-LAN (WoL) have been designed-in to satisfy energy-efficient environments.

All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed

through the MDC/MDIO interface.

FIGURE 1-1:

FUNCTIONAL BLOCK DIAGRAM

 2016 Microchip Technology Inc.

DS00002130A-page 5

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