ICL7660SIBAT 데이터 시트보기 (PDF) - Intersil
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ICL7660SIBAT Datasheet PDF : 13 Pages
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ICL7660S, ICL7660A
Detailed Description
The ICL7660S and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of two external capacitors, which may be
inexpensive 10µF polarized electrolytic types. The mode of
operation of the device may best be understood by
considering Figure 14, which shows an idealized negative
voltage converter. Capacitor C1 is charged to a voltage, V+,
for the half cycle, when switches S1 and S3 are closed.
(Note: Switches S2 and S4 are open during this half cycle).
During the second half cycle of operation, switches S2 and
S4 are closed, with S1 and S3 open, thereby shifting
capacitor C1 to C2 such that the voltage on C2 is exactly V+,
assuming ideal switches and no load on C2. The ICL7660S
and ICL7660A approach this ideal situation more closely
than existing non-mechanical circuits.
8
S1
2
S2
VIN
C1
3
3
S3
S4
4
C2
5
VOUT = -VIN
7
FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER
In the ICL7660S and ICL7660A, the four switches of
Figure 14 are MOS power switches; S1 is a P-Channel
device; and S2, S3 and S4 are N-Channel devices. The main
difficulty with this approach is that in integrating the switches,
the substrates of S3 and S4 must always remain reverse
biased with respect to their sources, but not so much as to
degrade their “ON” resistances. In addition, at circuit start-
up, and under output short circuit conditions (VOUT = V+),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this would result
in high power losses and probable device latch-up.
This problem is eliminated in the ICL7660S and ICL7660A by
a logic network that senses the output voltage (VOUT)
together with the level translators, and switches the
substrates of S3 and S4 to the correct level to maintain
necessary reverse bias.
The voltage regulator portion of the ICL7660S and
ICL7660A is an integral part of the anti-latchup circuitry;
however, its inherent voltage drop can degrade operation at
low voltages. Therefore, to improve low voltage operation,
the “LV” pin should be connected to GND, thus disabling the
regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latchup-proof operation
and to prevent device damage.
Theoretical Power Efficiency
Considerations
In theory, a voltage converter can approach 100% efficiency
if certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.
The ICL7660S and ICL7660A approach these conditions for
negative voltage conversion if large values of C1 and C2 are
used. ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined as shown in
Equation 1:
E
=
1--
2
C1(
V1
2
–
V2
2
)
(EQ. 1)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (see Figure 14)
compared to the value of RL, there will be a substantial
difference in the voltages, V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C1 in order to achieve maximum efficiency of
operation.
Do’s and Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods; however,
transient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C1 must
be connected to pin 2 of the ICL7660S and ICL7660A, and
the + terminal of C2 must be connected to GND.
5. If the voltage supply driving the ICL7660S and ICL7660A
has a large source impedance (25Ω to 30Ω), then a
2.2µF capacitor from pin 8 to ground may be required to
limit the rate of rise of input voltage to less than 2V/µs.
6. If the input voltage is higher than 5V and it has a rise rate
more than 2V/µs, an external Schottky diode from VOUT
to CAP- is needed to prevent latchup (triggered by
forward biasing Q4’s body diode) by keeping the output
(pin 5) from going more positive than CAP- (pin 4).
7. User should ensure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch-up will
occur under these conditions. To provide additional
protection, a 1N914 or similar diode placed in parallel
with C2 will prevent the device from latching up under
these conditions, when the load on VOUT creates a path
to pull up VOUT before the IC is active (anode pin 5,
cathode pin 3).
8
FN3179.7
January 23, 2013
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