6N135TSDVM 데이터 시트보기 (PDF) - Fairchild Semiconductor
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6N135TSDVM Datasheet PDF : 15 Pages
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Electrical Characteristics (Continued)
(TA = 0 to 70°C unless otherwise specified. Typical values are measured at TA = 25°C and VCC = 5V.)
Switching Characteristics (VCC = 5V)
Symbol Parameter
Test Conditions
tPHL Propagation Delay TA = 25°C, RL = 4.1kΩ,
Time to Logic LOW IF = 16mA(6) (Fig. 7)
RL = 1.9kΩ, IF = 16mA,
TA = 25°C(7) (Fig. 7)
RL = 4.1kΩ, IF = 16mA(6) (Fig. 7)
RL = 1.9kΩ, IF = 16mA(7) (Fig. 7)
tPLH Propagation Delay TA = 25°C, (RL = 4.1kΩ,
Time to Logic HIGH IF = 16mA(6) (Fig. 7)
RL = 1.9kΩ, IF = 16mA(7) (Fig. 7)
TA = 25°C
RL = 4.1kΩ, IF = 16mA(6) (Fig. 7)
RL = 1.9kΩ, IF = 16mA(7) (Fig. 7)
|CMH|
Common Mode
Transient
Immunity at
Logic High
|CML|
Common Mode
Transient
Immunity at
Logic Low
IF = 0mA, VCM = 10VP-P,
RL = 4.1kΩ, TA = 25°C(8) (Fig. 8)
IF = 0mA, VCM = 10VP-P,
RL = 1.9kΩ, TA = 25°C(8) (Fig. 8)
IF = 0mA, VCM = 1,500VP-P,
RL = 1.9kΩ, TA = 25°C(8) (Fig. 8)
IF = 16mA, VCM = 10VP-P,
RL = 4.1kΩ, TA = 25°C(8) (Fig. 8)
IF = 16mA, VCM = 10VP-P,
RL = 1.9kΩ(8) (Fig. 8)
IF = 0mA, VCM = 1,500VP-P,
RL = 1.9kΩ, TA = 25°C(8) (Fig. 8)
Device
6N135M
HCPL2530M
6N136M
HCPL4503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL2531M
Min.
Typ. Max. Unit
0.23 1.5 µs
0.25 0.8 µs
2.0 µs
1.0 µs
0.45 1.5 µs
0.26 0.8 µs
2.0 µs
1.0 µs
10,000
10,000
V/µs
V/µs
HCPL4503M 15,000 50,000
6N135M
HCPL2530M
6N136M
HCPL2531M
10,000
10,000
V/µs
V/µs
HCPL4503M 15,000 50,000
Notes:
6. The 4.1kΩ load represents 1 LSTTL unit load of 0.36mA and 6.1kΩ pull-up resistor.
7. The 1.9kΩ load represents 1 TTL unit load of 1.6mA and 5.6kΩ pull-up resistor.
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge
of the common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge
of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8V).
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.6
5
www.fairchildsemi.com
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