KSZ8895FMQ 데이터 시트보기 (PDF) - Micrel

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KSZ8895FMQ

Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface

Micrel 

Micrel, Inc.

KSZ8895MQ/RQ/FMQ

List of Figures

Figure 1. Typical Straight Cable Connection ............................................................................................................... 26

Figure 2. Typical Crossover Cable Connection ........................................................................................................... 27

Figure 3. Auto-Negotiation ........................................................................................................................................... 28

Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 33

Figure 5. Destination Address Resolution Flow Chart, Stage 2................................................................................... 34

Figure 6. 802.1p Priority Field Format.......................................................................................................................... 41

Figure 7. Tail Tag Frame Format .................................................................................................................................. 44

Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram ................................................................ 48

Figure 9. SPI Write Data Cycle .................................................................................................................................... 49

Figure 10. SPI Read Data Cycle .................................................................................................................................. 49

Figure 11. SPI Multiple Write ....................................................................................................................................... 50

Figure 12. SPI Multiple Read ....................................................................................................................................... 50

Figure 13. EEPROM Interface Input Receive Timing Diagram.................................................................................. 105

Figure 14. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 105

Figure 15. SNI Input Timing ....................................................................................................................................... 106

Figure 16. SNI Output Timing .................................................................................................................................... 106

Figure 17. MAC Mode MII Timing – Data Received from MII .................................................................................... 107

Figure 18. MAC Mode MII Timing – Data Transmitted from MII ................................................................................ 107

Figure 19. PHY Mode MII Timing – Data Received from MII..................................................................................... 108

Figure 20. PHY Mode MII Timing – Data Transmitted from MII................................................................................. 108

Figure 21. RMII Timing – Data Received from RMII .................................................................................................. 109

Figure 22. RMII Timing – Data Transmitted to RMII .................................................................................................. 109

Figure 23. SPI Input Timing ....................................................................................................................................... 110

Figure 24. SPI Output Timing..................................................................................................................................... 111

Figure 25: Auto-Negotiation Timing ........................................................................................................................... 112

Figure 26. MDC/MDIO Timing.................................................................................................................................... 113

Figure 27. Reset Timing ............................................................................................................................................. 114

Figure 28. Recommended Reset Circuit .................................................................................................................... 115

Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 115

January 22, 2013

11

Revision 1.6

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