KSZ8895FMQ 데이터 시트보기 (PDF) - Micrel
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KSZ8895FMQ Datasheet PDF : 118 Pages
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Micrel, Inc.
Features
Advanced Switch Features
• IEEE 802.1q VLAN support for up to 128 active VLAN
groups (full-range 4096 of VLAN IDs).
• Static MAC table supports up to 32 entries.
• VLAN ID tag/untag options, per port basis
• IEEE 802.1p/q tag insertion or removal on a per port basis
based on ingress port (egress).
• Programmable rate limiting at the ingress and egress on a
per port basis.
• Jitter-free per packet based rate limiting support.
• Broadcast storm protection with percentage control (global
and per port basis).
• IEEE 802.1d rapid spanning tree protocol RSTP support.
• Tail tag mode (1 byte added before FCS) support at Port 5
to inform the processor which ingress port receives the
packet.
• 1.4Gbps high-performance memory bandwidth and shared
memory-based
switch
fabric
with
fully
non-blocking configuration.
• Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII
for MAC 5 and P5-MII/RMII for PHY 5.
• Enable/Disable option for huge frame size up to 2000
Bytes per frame.
• IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
• IPv4/IPv6 QoS support.
• Support unknown unicast/multicast address and unknown
VID packet filtering.
• Self-address filtering.
Comprehensive Configuration Register Access
• Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
• High speed SPI (up to 25MHz) and I2C master Interface to
all internal registers.
• I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
• Control registers configurable on the fly (port-priority,
802.1p/d/q, AN).
QoS/CoS Packet Prioritization Support
• Per port, 802.1p and DiffServ-based.
• 1/2/4-queue QoS prioritization selection.
• Programmable weighted fair queuing for ratio control.
• Re-mapping of 802.1p priority field per port basis.
KSZ8895MQ/RQ/FMQ
Integrated Five-Port 10/100 Ethernet Switch
• New generation switch with five MACs and five PHYs with
fully compliant with IEEE 802.3u standard.
• PHYs designed with patented enhanced mixed-signal
technology.
• Non-blocking switch fabric assures fast packet delivery by
utilizing a 1K MAC address lookup table and a store-and-
forward architecture.
• On-chip 64Kbyte memory for frame buffering (not shared
with 1K unicast address table).
• Full duplex IEEE 802.3x flow control (PAUSE) with force
mode option.
• Half-duplex back pressure flow control.
• HP Auto MDI/MDI-X and IEEE Auto crossover support.
• SW-MII interface supports both MAC mode and PHY
mode.
• 7-wire serial network interface (SNI) support for legacy
MAC.
• Per port LED Indicators for link, activity, and 10/100
speed.
• Register port status support for link, activity, full/half
duplex and 10/100 speed.
• On-chip terminations and internal biasing technology for
cost down and lowest power consumption.
Switch Monitoring Features
• Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port or MII.
• MIB counters for fully compliant statistics gathering 34 MIB
counters per port.
• Loop-back support for MAC, PHY and remote diagnostic
of failure.
• Interrupt for the link change on any ports.
Low Power Dissipation
• Full-chip hardware power-down.
• Full-chip software power-down and per port software
power down.
• Energy-detect mode support < 100mW full chip-power
consumption when all ports have no activity.
• Very low full chip power consumption (<0.5W), without
extra power consumption on transformers.
• Dynamic clock tree shutdown feature.
• Voltages: Single 3.3V supply with 3.3V VDDIO and
Internal 1.2V LDO controller enabled, or external 1.2V
LDO solution.
– Analog VDDAT 3.3V only.
– VDDIO support 3.3V, 2.5V and 1.8V.
– Low 1.2V core power .
• 0.13µm CMOS technology.
• Commercial temperature range: 0°C to +70°C.
• Industrial Temperature Range: -40°C to +85°C.
• Available in 128-pin PQFP, lead-free package.
January 22, 2013
2
Revision 1.6
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