M52743BSP 데이터 시트보기 (PDF) - Renesas Electronics
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M52743BSP Datasheet PDF : 26 Pages
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M52743BSP
I2C BUS Control Section SDA, SCL Characteristics
Item
Min. input LOW voltage
Max. input HIGH voltage
SCL clock frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated
The LOW period of the clock
The HIGH period of the clock
Set up time for start condition (Only relevant for a repeated start condition)
Hold time DATA
Set-up time DATA
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Set-up time for stop condition
Symbol
VIL
VIH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
Min.
−0.5
3.0
0
4.7
4.0
4.7
4.0
4.7
0
250
4.0
Timing Chart
VIH
SDA
VIL
tr, tf
tHD: STA
tSU: DAT
tHD: DAT
tSU: STA
tSU: STO
Max.
1.5
5.5
100
1000
300
tBUF
Unit
V
V
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
VIH
SCL
VIL
S
tLOW
tHIGH
S
P
S
REJ03F0193-0201 Rev.2.01 Mar 31, 2008
Page 16 of 25
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