MT48LC16M8A2TG-75LAAT 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT48LC16M8A2TG-75LAAT

Automotive SDR SDRAM

Micron Technology 

128Mb: x4, x8, x16 Automotive SDRAM

Features

List of Figures

Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 16 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 15

Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ...................................................... 16

Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 17

Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 20

Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 21

Figure 13: ACTIVE Command ........................................................................................................................ 31

Figure 14: READ Command ........................................................................................................................... 32

Figure 15: WRITE Command ......................................................................................................................... 33

Figure 16: PRECHARGE Command ................................................................................................................ 34

Figure 17: Initialize and Load Mode Register .................................................................................................. 41

Figure 18: Mode Register Definition ............................................................................................................... 43

Figure 19: CAS Latency .................................................................................................................................. 46

Figure 20: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 47

Figure 21: Consecutive READ Bursts .............................................................................................................. 49

Figure 22: Random READ Accesses ................................................................................................................ 50

Figure 23: READ-to-WRITE ............................................................................................................................ 51

Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 52

Figure 25: READ-to-PRECHARGE .................................................................................................................. 52

Figure 26: Terminating a READ Burst ............................................................................................................. 53

Figure 27: Alternating Bank Read Accesses ..................................................................................................... 54

Figure 28: READ Continuous Page Burst ......................................................................................................... 55

Figure 29: READ – DQM Operation ................................................................................................................ 56

Figure 30: WRITE Burst ................................................................................................................................. 57

Figure 31: WRITE-to-WRITE .......................................................................................................................... 58

Figure 32: Random WRITE Cycles .................................................................................................................. 59

Figure 33: WRITE-to-READ ............................................................................................................................ 59

Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 60

Figure 35: Terminating a WRITE Burst ............................................................................................................ 61

Figure 36: Alternating Bank Write Accesses ..................................................................................................... 62

Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 63

Figure 38: WRITE – DQM Operation ............................................................................................................... 64

Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 66

Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 67

Figure 41: READ With Auto Precharge ............................................................................................................ 68

Figure 42: READ Without Auto Precharge ....................................................................................................... 69

Figure 43: Single READ With Auto Precharge .................................................................................................. 70

Figure 44: Single READ Without Auto Precharge ............................................................................................. 71

Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 72

Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 72

Figure 47: WRITE With Auto Precharge ........................................................................................................... 73

Figure 48: WRITE Without Auto Precharge ..................................................................................................... 74

Figure 49: Single WRITE With Auto Precharge ................................................................................................. 75

Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 76

PDF: 09005aef84baf515

128mb_x4x8x16_ait-aat_sdram.pdf - Rev. C 1/14 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 1999 Micron Technology, Inc. All rights reserved.

Share Link: