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CS62180B-IL 데이터 시트보기 (PDF) - Cirrus Logic

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CS62180B-IL
CIRRUS
Cirrus Logic CIRRUS
CS62180B-IL Datasheet PDF : 50 Pages
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CS62180B
HOST MODE
Serial Interface
For applications in which the device is to interface
with a host processor, the CS62180B can
be configured to run in host modeby tying the
Serial Port Select pin (SPS) to the +5V supply
(VDD). This allows access to the serial port,
providing a large number of configuration options
via the 16 on-chip control and status registers.
Serial read/write timing, controlled by SCLK, is
entirely independent of the transmit and receive
timing. This allows the host microcontroller to
monitor the status register and counters, modify
configuration options, and issue commands asyn-
chronously with the T1 system. A serial timing
overview is provided in Figure 1.
All data transfers are initiated by setting Chip Se-
lect (CS) low. Any read or write to the serial port is
initiated by writing an 8-bit command word. The
command word consists of 4 separate fields (see
Figure 2). When reading from the port, data is out-
put on the falling edge of SCLK, and held until the
next falling edge.
All data is written to and read from the port LSB
first. When writing to the port, SDI input data is
sampled on the rising edge of SCLK.
D0 (LSB) is the R/W field, and specifies whether
the current operation is to be a read or a write: 1 =
read, 0 = write. The second 4 bits (D1 - D4) con-
tain the address field. Written LSB first, they
specify which of the sixteen registers to access. D5
(Device Select) should be set to zero when address-
ing the CS62180B. However, if the CS62180B
shares the same serial interface lines with a
Cirrus TI Line Interface (see Figure 3), D5 will be
set to a "1" when addressing the Line Interface device.
The CS62180B will ignore any read/write
commandswith a "1" in D5,
allowing both parts to share CS.
D6 is reserved, and must be set to 0 for normal
operation.
CS
SCLK
SDI
SDO
R/W ADD0 ADD1 ADD2 ADD3 0
0 BM
Write Address Command Byte (ACB)
D0 D1 D2 D3 D4 D5 D6 D7
Read or Write Register Data
D0 D1 D2 D3 D4 D5 D6 D7
Figure 1. Serial Read/Write Timing
7 (MSB) 6
BM
0
0 Individual
1 Burst
Set to "0"
5
4
DS ADD3
0 CS62180B
1
Crystal
LIU
(MSB)
3
2
ADD2 ADD1
Register Address Field
1
ADD0
(LSB)
0 (LSB)
R/W
0 Write
1 Read
Figure 2. Address Command Byte (ACB)
8
DS225PP2

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