Q67006-A9360 데이터 시트보기 (PDF) - Infineon Technologies

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Q67006-A9360

5-V Low-Drop Fixed Voltage Regulator

Infineon Technologies 

TLE 4270

Design Notes for External Components

An input capacitor CI is necessary for compensation of line influences. The resonant

circuit consisting of lead inductance and input capacitance can be damped by a resistor

of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of

the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of

< 3 Ω.

Reset Circuitry

If the output voltage decreases below 4.5 V, an external capacitor CD on pin 4 (D) will be

discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a

reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage

rises above the reset threshold, CD will be charged with constant current. After the

power-on-reset time the voltage on the capacitor reaches VDU and the reset output will

be set high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of CD.

Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

Cd which can be calculated as follows:

Cd = (td × Id)/∆V

Definitions: Cd = delay capacitor

td = reset delay time

Id = charge current, typical 5 mA

∆V = VDU, typical 1.9 V

VDU = upper delay switching threshold at Cd for reset delay time

td = ∆V × CD/ID

The reset reaction time trr is the time it takes the voltage regulator to set the reset out

LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs

for delay capacitor of 47 nF. For other values for Cd the reaction time can be estimated

using the following equation:

trr ≈ 20 s/F × Cd

Data Sheet Version 1.1

9

2000-01-09

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