FM24CL64B 데이터 시트보기 (PDF) - Cypress Semiconductor
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FM24CL64B Datasheet PDF : 18 Pages
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FM24CL64B
Figure 9. Multi-Byte Write
Start
By Master
Address & Data
Stop
S
Slave Address 0 A
Address MSB
A
Address LSB
A
Data Byte
A
Data Byte
AP
By F-RAM
Acknowledge
Read Operation
There are two basic types of read operations. They are current
address read and selective address read. In a current address
read, the FM24CL64B uses the internal address latch to supply
the address. In a selective read, the user performs a procedure
to set the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24CL64B uses an internal latch to
supply the address for a read operation. A current address read
uses the existing value in the address latch as a starting place
for the read operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master supplies a
slave address with the LSB set to a ‘1’. This indicates that a read
operation is requested. After receiving the complete slave
address, the FM24CL64B will begin shifting out data from the
current address on the next clock. The current address is the
value held in the internal address latch.
Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
address read with multiple byte transfers. After each byte the
internal address counter will be incremented.
Note Each time the bus master acknowledges a byte, this
indicates that the FM24CL64B should read out the next
sequential byte.
There are four ways to properly terminate a read operation.
Failing to properly terminate the read will most likely create a bus
contention as the FM24CL64B attempts to read out additional
data onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the 9th clock
cycle and a STOP in the 10th clock cycle. This is illustrated in
the diagrams below. This is preferred.
2. The bus master issues a no-acknowledge in the 9th clock
cycle and a START in the 10th.
3. The bus master issues a STOP in the 9th clock cycle.
4. The bus master issues a START in the 9th clock cycle.
If the internal address reaches 1FFFh, it will wrap around to
0000h on the next read cycle. Figure 10 and Figure 11 below
show the proper operation for current address reads.
Figure 10. Current Address Read
By Master
Start
Address
No
Acknowledge
Stop
S
Slave Address 1 A
Data Byte
1P
By F-RAM
Acknowledge Data
By Master
Start
Figure 11. Sequential Read
Address
Acknowledge
No
Acknowledge
S
Slave Address 1 A
Data Byte
A
Data Byte
1P
By F-RAM
Acknowledge
Data
Stop
Document Number: 001-84458 Rev. *I
Page 7 of 18
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