AZ10LVEL33DR1 데이터 시트보기 (PDF) - AZ Microtek

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AZ10LVEL33DR1

ECL/PECL ÷4 Divider

AZ Microtek 

AZ10LVEL33

AZ100LVEL33

AZ10/100LVEL33L

RESET NC NC VCC

16 15 14 13

PACKAGE PINOUTS

TOP VIEW

AZ100LVEL33N

NC 1

12 NC

RESET 1

CLK 2

CLK 3

MLP16

11 Q

10 Q

VBB 4

5

6

NC NC

9 NC

7

8

VEE 10K

CLK 2

CLK 3

VBB 4

MLP 8

8 VCC

7Q

6Q

5 VEE

100K Mode: Leave the 10K pin open (NC)

10K Mode: Connect the 10K pin to VEE

Bottom Center Pad may be left open or tied to VEE.

Bottom Center Pad may be left open or tied to VEE.

AZ10LVEL33D

AZ100LVEL33D

AZ10LVEL33T

AZ100LVEL33T

RESET 1

8 VCC

CLK 2

CLK 3

SOIC 8

TSSOP 8

7Q

6Q

VBB 4

5 VEE

April 2007 * REV - 9

www.azmicrotek.com

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