P89C51RD2 데이터 시트보기 (PDF) - Philips Electronics

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P89C51RD2

80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

Philips Electronics 

Philips Semiconductors

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

Table 1. Special Function Registers (Continued)

SYMBOL

DESCRIPTION

DIRECT

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

LSB

RESET

VALUE

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

CY

AC

F0

RS1 RS0

OV

F1

P

00000000B

RCAP2H# Timer 2 Capture High

CBH

00H

RCAP2L# Timer 2 Capture Low

CAH

00H

SADDR# Slave Address

A9H

00H

SADEN# Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

SCON*

SP

Serial Control

Stack Pointer

TCON* Timer Control

99H

9F

9E

9D

9C

9B

9A

99

98H SM0/FE SM1 SM2 REN TB8 RB8

TI

81H

8F

8E

8D

8C

8B

8A

89

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

xxxxxxxxB

98

RI 00H

07H

88

IT0 00H

CF

CE

CD

CC

CB

CA

C9

C8

T2CON* Timer 2 Control

C8H

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H

T2MOD# Timer 2 Mode Control

C9H

–

–

–

–

–

– T2OE DCEN xxxxxx00B

TH0

Timer High 0

8CH

00H

TH1

Timer High 1

8DH

00H

TH2#

Timer High 2

CDH

00H

TL0

Timer Low 0

8AH

00H

TL1

Timer Low 1

8BH

00H

TL2#

Timer Low 2

CCH

00H

TMOD Timer Mode

89H GATE C/T

M1

M0 GATE C/T

M1

M0 00H

WDTRST Watchdog Timer Reset A6H

* SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

– Reserved bits.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an

on-chip oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. Minimum and maximum

high and low times specified in the data sheet must be observed.

This device is configured at the factory to operate using 6 clock

periods per machine cycle, referred to in this datasheet as “6 clock

mode”. (This yields performance equivalent to twice that of standard

80C51 family devices). It may be optionally configured on

commercially-available EPROM programming equipment to operate

at 12 clocks per machine cycle, referred to in this datasheet as

“12 clock mode”. Once 12 clock mode has been configured, it

cannot be changed back to 6 clock mode.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator

periods in 12 clock mode), while the oscillator is running. To ensure a

good power-on reset, the RST pin must be high long enough to allow

the oscillator time to start up (normally a few milliseconds) plus two

machine cycles. At power-on, the voltage on VCC and RST must

come up at the same time for a proper start-up. Ports 1, 2, and 3 will

asynchronously be driven to their reset condition when a voltage

above VIH1 (min.) is applied to RESET.

The value on the EA pin is latched when RST is deasserted and has

no further effect.

1999 Sep 23

9

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