General
Table 8. Power mode transition operating behaviors (continued)
Symbol Description
• VLLS3 → RUN
Min.
Typ.
Max.
Unit
—
93
104
μs
• LLS → RUN
• VLPS → RUN
• STOP → RUN
—
7.5
8
μs
—
7.5
8
μs
—
7.5
8
μs
Notes
2.2.5 Power consumption operating behaviors
NOTE
The while (1) test is executed with flash cache enabled.
Table 9. Power consumption operating behaviors
Symbol Description
IDDA Analog supply current
IDD_RUNCO Running CoreMark in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
Min.
—
Typ.
Max.1
Unit
—
See note
mA
—
5.76
6.40
mA
6.04
6.68
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
3.21
3.85
mA
3.49
4.13
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
• at 105 °C
—
6.45
7.09
mA
6.75
7.39
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
3.95
4.59
mA
4.23
4.87
mA
Table continues on the next page...
Notes
2
3
—
3
3,
Kinetis KL27 With Up To 256 KB Flash, Rev3, 08/2014.
9
Freescale Semiconductor, Inc.