M62320FP 데이터 시트보기 (PDF) - Renesas Electronics

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M62320FP

8-bit I/O Expander for I²C BUS

Renesas Electronics 

M62320P/FP

Digital Data Format

1. Write mode: I2C BUS data input to parallel data output

First

S Slave address W A I/O setting A 8-bit data A 8-bit data A

2. Read mode: Parallel data input to I2C BUS data output

First

S Slave address W A 8-bit data A 8-bit data A 8-bit data A …..

Transmission from Master (MCU etc.) to Slave (M62320)

Transmission from Slave (M62320) to Master (MCU etc.)

Last

…..

AP

Last

8-bit data A P

• S: Start condition

While SCL level is high, SDA line level should be changed from high to low.

• Slave address

First

MSB

0

1

1

Last

LSB

1

A2 A1 A0

Note:

Lower three bits (A0, A1, A2) are a programmable

address. This IC is accessed only when the lower 3

bits data of slave address coincide with the data of

CS0 to CS2. (refer to the right table)

Chip select data

MSB

LSB

A2

A1

A0

CS2 CS1 CS0

0

0

0

L

L

L

0

0

1

L

L

H

0

1

0

L

H

L

:

:

:

:

:

:

1

1

1

H

H

H

Note: L = Low, H = High

• W: Write (SDA = Low), R: Read (SDA = High)

• A: Acknowledge bit

• I/O setting data (I/O setting of parallel data I/O terminals.)

First

Last

MSB

LSB

P7 P6 P5 P4 P3 P2 P1 P0

Note: DATA INPUT from parallel data terminals = Low

DATA OUTPUT to parallel data terminals = High

Each bit data corresponds to the I/O state of the parallel data terminals.

• 8-bit data

First

Last

MSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0

• P: Stop condition

While SCL level is high, SDA level should be changed from low to high.

REJ03D0863-0300 Rev.3.00 Mar 25, 2008

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