I43T16256A-125KBLR 데이터 시트보기 (PDF) - Integrated Silicon Solution
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I43T16256A-125KBLR Datasheet PDF : 88 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
CK,CK#
VDD,VDDQ
Ta
Tb
((
)( ()
))
((
))
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
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((
((
((
((
((
((
((
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
))
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tCKSRX
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RESET#
CKE
T=200µS
T=5(0(0µS
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tIS
Tmin=10nS
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)( ()
)( ()
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)( ()
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)( ()
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)( ()
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tDLLK
((
))
((
)( () Valid
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((
CMMAND
)( ()
))
((
BA
)( ()
))
((
ODT
)( ()
))
tXPR
tIS
tMRD
tMRD
tMRD
tMOD
tZQinit
((
((
((
((
((
((
((
((
)( ()
1) )( () MRD )( () MRD )( () MRD )( () MRD )( () ZQCL )( () 1) )( () Valid
))
))
))
))
))
))
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))
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((
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((
((
((
)( ()
)( () MR2 )( () MR3 )( () MR1 )( () MR0 )( ()
)( ()
)( () Valid
))
))
))
))
))
))
))
))
tIS
tIS
((
((
((
((
)( ()
Stat)(i()c LOW in case RTT_Nom is enabled at time Tg, otherwise static HIG)( H() or LOW )( () Valid
))
))
))
))
RTT
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Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
( ( Time
) ) Break
Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping
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DON’T
CARE
Integrated Silicon Solution, Inc. – www.issi.com –
8
Rev. I
04/27/2017
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