74LVT16244G 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74LVT16244G Datasheet PDF : 7 Pages
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Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Logic Diagram
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Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
NC
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0 NC OE1 OE2 NC
I0
B
O2
O1
NC NC
I1
I2
C
O4
O3 VCC VCC
I3
I4
D
O6
O5 GND GND I5
I6
E
O8
O7 GND GND I7
I8
F
O10 O9 GND GND I9
I10
G
O12
O11 VCC VCC
I11
I12
H
O14 O13 NC NC
I13
I14
J
O15 NC OE4 OE3 NC
I15
Truth Table
Inputs
OE1
I0–I3
L
L
L
H
H
X
Inputs
OE2
I4–I7
L
L
L
H
H
X
Inputs
OE3
I8–I11
L
L
L
H
H
X
Inputs
OE4
L
L
H
H High Voltage Level
L Low Voltage Level
X Immaterial
Z High Impedance
I12–I15
L
H
X
Outputs
O0–O3
L
H
Z
Outputs
O4–O7
L
H
Z
Outputs
O8–O11
L
H
Z
Outputs
O12–O15
L
H
Z
Functional Description
The LVT16244 and LVTH16244 contain sixteen non-invert-
ing buffers with 3-STATE outputs. The device is nibble
(4-bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation.
2
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