CL1K30FC256-1 데이터 시트보기 (PDF) - Clear Logic

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CL1K30FC256-1

LIBERATOR

Clear Logic 

Additional

Information

LIBERATOR CL1K30 (PRELIMINARY)

For further information on designing with the CL1K LPLD®

family, please refer to the following documents (all CL10K

documents also pertain to the CL1K devices):

u AN-01: Requesting a First Article. This document provides

instructions on how to request first articles by submitting a

bitstream file to Clear Logic's web site.

u AN-02: Clear Logic Packaging Guide. This document provides

specifications and drawings for packages used by the CL10K

family and other Clear Logic devices.

u AN-13: LIBERATOR -- A New Way To Design. This document

describes the most efficient path for custom logic designs up

to 200K gates using FPGA design techniques and going to

production with Clear Logic.

u AN-14: CL10K Technology White Paper. This document

outlines the technologies employed by the LIBERATOR

family.

u AN-15: LIBERATOR System Configuration. This document

contains a detailed discussion of all aspects of configuring

CL10K-based systems.

u AN-16: Introduction to the Clear Logic Verilog Model

Generator. Clear Logic now has Verilog models of your FPGA

converted design. Learn what it is and how it can help you.

u AN-17: Clear Logic LIBERATOR Design Models. This

document outlines the capabilities and freedom available in

the Clear Logic Verilog and VHDL design models.

u AN-18: Debugging Designs Using Clear Logic Models. This

document shows the enhanced troubleshooting capabilities

that the Clear Logic LIBERATOR Verilog/VHDL design

models bring to the system debugging process.

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