P90CL301 데이터 시트보기 (PDF) - Philips Electronics
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P90CL301 Datasheet PDF : 92 Pages
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Philips Semiconductors
Low voltage 16-bit microcontroller
Preliminary specification
P90CL301BFH (C100)
6.2.1 CHIP SELECT CONTROL REGISTERS (CS0N TO CS7N)
Table 3 Chip Select Control Registers CS0N to CS7N (address FFFF 8A00H to FFFF 8A0CH)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
M22 M21 M20 M19 RW1 RW0 MD1 MD0 A23 A22 A21 A20 A19 WS2 WS1 WS0
Table 4 Description of CS0N to CS7N bits
BIT
15 to 12
11 to 10
9 to 8
7 to 3
2 to 0
SYMBOL
DESCRIPTION
M22 to M19 Address mask for block size selection; see Table 5.
RW1 to RW0 Read/Write bus control (R/W); see Table 6.
MD1 to MD0 MODE selection; see Table 7.
A23 to A19 Decoded base address; this should be a multiple of the block size (other codes are
reserved for test or reset state); after reset: A23 to A19 = 11111 except for CSBT.
WS2 to WS0 Wait states 0 to 6 (see Table 8); 7 wait states for DTACK to be pulled LOW by the
external address decoding circuitry. The default value after reset is ‘110B’ for CSBT and
‘111B’ for the other chip-selects.
Table 5 Address mask for block size selection
M22 M21 M20 M19
BLOCK SIZE
0
0
0
0 512 kbytes
0
0
0
1 1 Mbyte
0
0
1
1 2 Mbytes
0
1
1
1 4 Mbytes
1
1
1
1 8 Mbytes; default value
after a CPU reset
Table 6 Read/Write bits (R/W)
RW1 RW0
FUNCTION
0
0 Read only with length of AS
0
1 Write only with length of DS
1
0 Write only with length of AS
1
1 Read/write with length of AS; default
value after a CPU reset
Table 8 Wait states selection
WS2
0
0
0
0
1
1
1
WS1
0
0
1
1
0
0
1
WS0
0
1
0
1
0
1
0
WAIT STATES
0
1
2
3
4
5
6(1)
Note
1. The default value after a CPU reset.
Table 7 Mode selection
MD1
0
0
1
1
MD0
0
1
0
1
FUNCTION
Alternate function
Low byte access only
High byte access only
Word access; default value after a CPU
reset
1996 Dec 11
9
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