74VCX162839MTDX 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74VCX162839MTDX
Fairchild Semiconductor
74VCX162839MTDX Datasheet PDF : 7 Pages
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March 1998
Revised December 2000
74VCX162839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26Ω Series Resistors in the Outputs
General Description
The VCX162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX162839 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX162839 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74VCX162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in the outputs
s tPD (CLK to On)
4.1 ns max for 3.0V to 3.6V VCC
5.8 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162839MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I0–I19
O0–O19
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
© 2000 Fairchild Semiconductor Corporation DS500127
www.fairchildsemi.com
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