MC100E310FN(2002) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100E310FN Datasheet PDF : 8 Pages
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MC100E310
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0 Q0 Q1 VCCO Q1 Q2 Q2
25 24 23 22 21 20 19
VEE 26
18 Q3
CLK_SEL 27
17 Q3
CLKa 28
VCC 1
CLKa 2
16 Q4
Pinout: 28–Lead PLCC
(Top View)
15
VCCO
14 Q4
VBB 3
13 Q5
CLKb 4
12 Q5
5 6 7 8 9 10 11
CLKb NC Q7 VCCO Q7 Q6 Q6
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
CLKa
CLKa
CLKb
CLKb
CLK_SEL
VBB
PIN DESCRIPTION
PIN
FUNCTION
CLKa, CLKb;
ECL Differential Input Pairs
CLKa, CLKb
ECL Differential Input Pairs
Q0:7; Q0:7
ECL Differential Outputs
CLK_SEL
ECL Input Clock Select
VBB
VCC, VCCO
VEE
NC
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
FUNCTION TABLE
CLK_SEL
Input Clock
0
CLKa Selected
1
CLKb Selected
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