FDS6612A 데이터 시트보기 (PDF) - Fairchild Semiconductor

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FDS6612A

Single N-Channel, Logic-Level, PowerTrench MOSFET

Fairchild Semiconductor 

Electrical Characteristics

Symbol

Parameter

TA = 25°C unless otherwise noted

Test Conditions

Min Typ Max Units

Off Characteristics

BVDSS

∆BVDSS

∆TJ

IDSS

Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA

30

Breakdown Voltage Temperature

Coefficient

ID = 250 µA, Referenced to 25°C

Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V

VDS = 24 V, VGS = 0 V, TJ=55°C

IGSS

Gate–Body Leakage

VGS = ±20 V, VDS = 0 V

V

26

mV/°C

1

µA

10

µA

±100 nA

On Characteristics (Note 2)

VGS(th)

Gate Threshold Voltage

∆VGS(th)

∆TJ

RDS(on)

Gate Threshold Voltage

Temperature Coefficient

Static Drain–Source

On–Resistance

ID(on)

On–State Drain Current

gFS

Forward Transconductance

VDS = VGS, ID = 250 µA

1 1.9

3

V

ID = 250 µA, Referenced to 25°C

–4.4

mV/°C

VGS = 10 V, ID = 8.4 A

VGS = 4.5 V, ID = 7.2 A

VGS= 10 V, ID = 8.4 A, TJ=125°C

19 22

mΩ

24 30

25 37

VGS = 10 V, VDS = 5 V

20

A

VDS = 15 V, ID = 8.4 A

30

S

Dynamic Characteristics

Ciss

Input Capacitance

Coss

Output Capacitance

Crss

Reverse Transfer Capacitance

RG

Gate Resistance

VDS = 15 V,

f = 1.0 MHz

V GS = 0 V,

VGS = 15 mV, f = 1.0 MHz

560

pF

140

pF

55

pF

2.5

Ω

Switching Characteristics (Note 2)

td(on)

Turn–On Delay Time

tr

Turn–On Rise Time

td(off)

Turn–Off Delay Time

tf

Turn–Off Fall Time

Qg

Total Gate Charge

Qgs

Gate–Source Charge

Qgd

Gate–Drain Charge

VDD = 15 V,

VGS = 10 V,

ID = 1 A,

RGEN = 6 Ω

VDS = 15 V,

VGS = 5 V

ID = 8.4 A,

7

14

ns

5

10

ns

22 35

ns

3

6

ns

5.4 7.6

nC

1.7

nC

1.9

nC

Drain–Source Diode Characteristics and Maximum Ratings

IS

Maximum Continuous Drain–Source Diode Forward Current

VSD

Drain–Source Diode Forward

Voltage

VGS = 0 V,

IS = 2.1 A (Note 2)

trr

Diode Reverse Recovery Time

Qrr

Diode Reverse Recovery Charge IF = 8.4 A, diF/dt = 100 A/µs

2.1

A

0.77 1.2

V

19

nS

9

nC

Notes:

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.

a) 50°C/W when mounted

on a 1in2 pad of 2 oz

copper

2 Test: Pulse Width < 300µs, Duty Cycle < 2.0%

b) 125°C/W when mounted on a

minimum pad.

Scale 1 : 1 on letter size paper

FDS6612A Rev D (W)

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