Switching Waveforms (continued)
First Data Word Latency after Reset with Read and Write
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
WCLK
tDS
D0 –D8
D0(FIRST VALID WRITE)
D1
D2
WEN1
tENS
tFRL [17]
WEN2
(if applicable)
RCLK
EF
REN1,
REN2
tSKEW1
tREF
tA
Q0 –Q8
OE
tOLZ
tOE
D3
D4
tA[18]
D0
D1
Notes:
17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK
+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06013 Rev. *B
Page 10 of 16