CY7C1061AV33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1061AV33 Datasheet PDF : 17 Pages
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CY7C1061AV33
AC Switching Characteristics
Over the Operating Range
Parameter [8]
Description
Read Cycle
tpower
VCC(typical) to the first access [9]
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW/CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
OE LOW to Low Z
OE HIGH to High Z [10]
CE1 LOW/CE2 HIGH to Low Z [10]
CE1 HIGH/CE2 LOW to High Z [10]
CE1 LOW/CE2 HIGH to Power Up [11]
CE1 HIGH/CE2 LOW to Power Down [11]
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle [12, 13]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE1 LOW/CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [10]
WE LOW to High Z [10]
Byte Enable to End of Write
-10
Unit
Min
Max
1
–
ms
10
–
ns
–
10
ns
3
–
ns
–
10
ns
–
5
ns
1
–
ns
–
5
ns
3
–
ns
–
5
ns
0
–
ns
–
10
ns
–
5
ns
1
–
ns
–
5
ns
10
–
ns
7
–
ns
7
–
ns
0
–
ns
0
–
ns
7
–
ns
5.5
–
ns
0
–
ns
3
–
ns
–
5
ns
7
–
ns
Notes
8.
Test
and
conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the
F0igtour3e.03Vo,nanpdagoeut6p,uut nloleasdsinsgpoefctihfieedspoethceifriewdisIeO.L/IOH
9. This part has a voltage regulator that steps down the voltage from 3 V to 2 V internally. tpower time must be provided initially before a Read/Write operation is started.
10. ftHroZmOEs,tteHaZdCyE-,sttHaZteWvEo, lttHaZgBeE. and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 6. Transition is measured 200 mV
11. These parameters are guaranteed by design and are not tested.
12.
The internal Write
be LOW to initiate
time of the memory is defined by
a Write, and the transition of any
othf ethoevseerlsaigpnoaflCs Eca1nLtOerWmi(nCaEte2
HIGH) and WE LOW. Chip enables
the Write. The input data setup and
must be active and WE and byte
hold timing should be referenced
enables must
to the leading
edge of the signal that terminates the Write.
13. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05256 Rev. *L
Page 7 of 17
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