S25FL256SDSBHID00 데이터 시트보기 (PDF) - Spansion Inc.

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S25FL256SDSBHID00

MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Spansion Inc. 

Data Sheet

Figure 10.11 Write Registers (WRR) Command Sequence – 16 data bits . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 10.12 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 10.13 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 10.14 Clear Status Register (CLSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 10.15 AutoBoot Sequence (CR1[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 10.16 AutoBoot Sequence (CR1[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 10.17 AutoBoot Register Read (ABRD) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 10.18 AutoBoot Register Write (ABWR) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 10.19 Program NVDLR (PNVDLR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 10.20 Write VDLR (WVDLR) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 10.21 DLP Read (DLPRD) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 10.22 Read Command Sequence (3-byte Address, 03h [ExtAdd=0]) . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 10.23 Read Command Sequence (4-byte Address, 13h or 03h [ExtAdd=1]) . . . . . . . . . . . . . . . . . 93

Figure 10.24 Fast Read (FAST_READ) Command Sequence

(3-byte Address, 0Bh [ExtAdd=0, LC=10b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 10.25 Fast Read Command Sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=10b) . . . . . . 94

Figure 10.26 Fast Read Command Sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=11b) . . . . . . 94

Figure 10.27 Dual Output Read Command Sequence (3-byte Address, 3Bh [ExtAdd=0], LC=10b) . . . . . 95

Figure 10.28 Dual Output Read Command Sequence

(4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 10.29 Dual Output Read Command Sequence

(4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 10.30 Quad Output Read Command Sequence (3-byte Address, 6Bh [ExtAdd=0, LC=01b]). . . . . 96

Figure 10.31 Quad Output Read Command Sequence

(4-byte Address, 6Ch or 6Bh [ExtAdd=1, LC=01b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Figure 10.32 Quad Output Read Command Sequence

(4-byte Address, 6Ch or 6Bh [ExtAdd=1], LC=11b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Figure 10.33 Dual I/O Read Command Sequence (3-byte Address, BBh [ExtAdd=0], HPLC=00b). . . . . . 98

Figure 10.34 Dual I/O Read Command Sequence (4-byte Address, BBh [ExtAdd=1], HPLC=10b). . . . . . 98

Figure 10.35 Dual I/O Read Command Sequence

(4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Figure 10.36 Continuous Dual I/O Read Command Sequence

(4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b). . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 10.37 Quad I/O Read Command Sequence (3-byte Address, EBh [ExtAdd=0], LC=00b) . . . . . . 100

Figure 10.38 Continuous Quad I/O Read Command Sequence (3-byte Address), LC=00b. . . . . . . . . . . 101

Figure 10.39 Quad I/O Read Command Sequence

(4-byte Address, ECh or EBh [ExtAdd=1], LC=00b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Figure 10.40 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b. . . . . . . . . . . 102

Figure 10.41 DDR Fast Read Initial Access (3-byte Address, 0Dh [ExtAdd=0, EHPLC=11b]). . . . . . . . . 103

Figure 10.42 Continuous DDR Fast Read Subsequent Access

(3-byte Address [ExtAdd=0, EHPLC=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Figure 10.43 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b) . . . 104

Figure 10.44 Continuous DDR Fast Read Subsequent Access

(4-byte Address [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Figure 10.45 DDR Fast Read Subsequent Access (4-byte Address, HPLC=01b) . . . . . . . . . . . . . . . . . . 104

Figure 10.46 DDR Dual I/O Read Initial Access

(4-byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b) . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Figure 10.47 Continuous DDR Dual I/O Read Subsequent Access (4-byte Address, EHPLC= 01b). . . . 106

Figure 10.48 DDR Dual I/O Read (4-byte Address, BEh or BDh [ExtAdd=1], HPLC=00b) . . . . . . . . . . . 106

Figure 10.49 DDR Quad I/O Read Initial Access (3-byte Address, EDh [ExtAdd=0], HPLC=11b) . . . . . . 108

Figure 10.50 Continuous DDR Quad I/O Read Subsequent Access (3-byte Address,HPLC=11b) . . . . . 108

Figure 10.51 DDR Quad I/O Read Initial Access

(4-byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Figure 10.52 Continuous DDR Quad I/O Read Subsequent Access (4-byte Address, EHPLC=01b) . . . 109

Figure 10.53 Page Program (PP) Command Sequence (3-byte Address, 02h) . . . . . . . . . . . . . . . . . . . . 110

Figure 10.54 Page Program (4PP) Command Sequence (4-byte Address, 12h) . . . . . . . . . . . . . . . . . . . 111

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S25FL128S and S25FL256S

S25FL128S_256S_00_05 July 12, 2012

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